參數(shù)資料
型號: LMV339DR2G
廠商: ON Semiconductor
文件頁數(shù): 3/20頁
文件大?。?/td> 0K
描述: IC COMPARATOR GP LV QUAD 14-SOIC
標準包裝: 2,500
類型: 通用
元件數(shù): 4
輸出類型: 開路漏極
電壓 - 電源,單路/雙路(±): 2.7 V ~ 5 V
電壓 - 輸入偏移(最小值): 9mV @ 5V
電流 - 輸入偏壓(最小值): 0.001µA @ 5V
電流 - 輸出(標準): 84mA @ 5V
電流 - 靜態(tài)(最大值): 350µA
傳輸延遲(最大): 1.5µs
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
安裝類型: 表面貼裝
包裝: 帶卷 (TR)
LMV331, NCV331, LMV393, LMV339
http://onsemi.com
11
APPLICATION CIRCUITS
Basic Comparator Operation
The basic operation of a comparator is to compare two
input voltage signals, and produce a digital output signal by
determining which input signal is higher. If the voltage on
the noninverting input is higher, then the internal output
transistor is off and the output will be high. If the voltage on
the inverting input is higher, then the output transistor will
be on and the output will be low. The LMV331/393/339 has
an opendrain output stage, so a pullup resistor to a positive
supply voltage is required for the output to switch properly.
The size of the pullup resistor is recommended to be
between 1 k
W and 10 kW. This range of values will balance
two key factors; i.e., power dissipation and drive capability
for interface circuitry.
Figure 19 illustrates the basic operation of a comparator
and assumes dual supplies. The comparator compares the
input voltage (VIN) on the noninverting input to the
reference voltage (VREF) on the inverting input. If VINis less
than VREF, the output voltage (VO) will be low. If VIN is
greater than VREF, then VO will be high.
Figure 19.
+
+VREF
3.0 k
VO
+VIN
V+
0 V
VREF
VOUT
VIN
Time
V+
Comparators and Stability
A common problem with comparators is oscillation due to
their high gain. The basic comparator configuration in
Figure 19 may oscillate if the differential voltage between
the input pins is close to the device’s offset voltage. This can
happen if the input signal is moving slowly through the
comparator’s switching threshold or if unused channels are
connected to the same potential for termination of unused
channels. One way to eliminate output oscillations or
‘chatter’ is to include external hysteresis in the circuit
design.
Inverting Configuration with Hysteresis
An inverting comparator with hysteresis is shown in
Figure 20.
Figure 20. Inverting
Comparator with
Hysteresis
+VCC
+
R3
V+
RPULLUP
VO
RLOAD
R2
R1
VIN
When VIN is less than the voltage at the noninverting
node, V+, the output voltage will be high. When VIN is
greater than the voltage at V+, then the output will be low.
The hysteresis band (Figure 21) created from the resistor
network is defined as:
DV) + VT1 * VT2
where VT1 and VT2 are the lower and upper trip points,
respectively.
VT1
VT2
VIN
VO
VCC
0
Figure 21.
VT1 is calculated by assuming that the output of the
comparator is pulled up to supply when high. The
resistances R1 and R3 can be viewed as being in parallel
which is in series with R2 (Figure 22). Therefore VT1 is:
VT1 +
VCC R2
R1 R3 ) R2
VT2 is calculated by assuming that the output of the
comparator is at ground potential when low. The resistances
R2 and R3 can be viewed as being in parallel which is in
series with R1 (Figure 23). Therefore VT2 is:
VT2 +
VCC R2 R3
R1 ) R2 R3
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