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參數(shù)資料
| 型號(hào)： | LMK04010BISQE/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 29/65頁 |
| 文件大小： | 0K |
| 描述： | IC CLOCK COND 1.2GHZ W/PLL 48LLP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PowerWise® |
| 類型： | 時(shí)鐘調(diào)節(jié)器 |
| PLL： | 是 |
| 輸入： | LVCMOS |
| 輸出： | 2VPECL，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:5 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 1.296GHz |
| 除法器/乘法器： | 是/是 |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-LLP（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1275 (CN2011-ZH PDF) |
| 其它名稱： | LMK04010BISQEDKR |
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SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Setting this bit to 0 does not prevent PLL1 from locking the external oscillator to the reference clock input after
the latter input becomes valid.
Register 11
CLKinX_BUFTYPE: PLL1 CLKinX/CLKinX* Buffer Mode Control
The user may choose between one of two input buffer modes for the PLL1 reference clock inputs: either bipolar
junction differential or MOS. Both CLKinX and CLKinX* input pins must be AC coupled when driven differentially.
In single ended mode, the CLKinX* pin must be coupled to ground through a capacitor. The active CLKinX buffer
mode is selected by the CLKinX_TYPE bits programmed via the uWire interface.
Table 12. PLL1 CLKinX_BUFTYPE Mode Control Bits
b1
b0
CLKin1_TYPE
CLKin0_TYPE
0
BJT Differential
0
1
BJT Differential
MOS
1
0
MOS
BJT Differential
1
MOS
CLKin_SEL: PLL1 Reference Clock Selection and Revertive Mode Control Bits
This register allows the user to set the reference clock input that is used to lock PLL1, or to select an auto-
switching mode. The automatic switching modes are revertive or non-revertive. In either revertive or non-
revertive mode, CLKin0 is the initial default reference source for the auto-switching mode. When revertive mode
is active, the switching control logic will always select CLKin0 as the reference if it is active, otherwise it selects
CLKin1. When non-revertive mode is active, the switching logic will only switch the reference input if the currently
selected input fails.
Table 13 illustrates the control modes. Modes [1,0] and [1,1] are the auto-switching modes. The behavior of both
modes is tied to the state of the LOS signals for the respective reference clock inputs.
If the reference clock inputs are active prior to configuration of the device, then the normal programming
sequence described under General Programming Information can be used without modification. If it cannot be
guaranteed that the reference clocks are active prior to device programming, then the device programming
sequence should be modified in order to ensure that CLKin0 is selected as the default. Under this scenario, the
device should be programmed as described in General Programming Information, with CLKin_SEL bits
programmed to [0,0] in register R11. The other R11 fields for clock type and LOS timeout should be programmed
with the appropriate values for the given application. After the reference clock inputs have started, register R11
should be programmed a second time with the CLKin_SEL field modified to the set the desired mode. The clock
type field and LOS field values should remain the same.
Table 13. CLKin_SEL: Reference Clock Selection Bits
CLKin_SEL [1:0]
Function
b1
b0
0
Force CLKin0 / CLKin0* as PLL1 reference
0
1
Force CLKin1 / CLKin1* as PLL1 reference
1
0
Non-revertive. Auto-switching. CLKin0 is the default reference clock. If CLKin0 fails, CLKin1
is automatically selected if active. If CLKin0 restarts, CLKin1 remains as the selected
reference clock unless it fails, then CLKin0 is re-selected.
1
Revertive. Auto-switching. CLKin0 is the preferred reference clock and is selected when
active.
CLKinX_LOS
The CLKin0_LOS and CLKin1_LOS pins indicate the state of the respective PLL1 CLKinX reference input when
the CLKin_SEL bits are set set to either [1,0] or [1,1]. The detection logic that determines the state of the
reference inputs is sensitive to the frequency of the reference inputs and must be configured to operate with the
appropriate frequency range of the reference inputs, as described in the next section.
Copyright 2008–2011, Texas Instruments Incorporated
35
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| LMK04010BISQX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs |
| LMK04010BISQX/NOPB | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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