參數資料
型號: LMK04001BISQE/NOPB
廠商: National Semiconductor
文件頁數: 33/65頁
文件大?。?/td> 0K
描述: IC CLOCK COND 1.5GHZ W/PLL 48LLP
標準包裝: 1
系列: PowerWise®
類型: 時鐘調節(jié)器
PLL:
輸入: LVCMOS
輸出: LVCMOS,2VPECL,LVPECL
電路數: 1
比率 - 輸入:輸出: 2:7
差分 - 輸入:輸出: 是/是
頻率 - 最大: 1.57GHz
除法器/乘法器: 是/是
電源電壓: 3.15 V ~ 3.45 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-WFQFN 裸露焊盤
供應商設備封裝: 48-LLP(7x7)
包裝: 標準包裝
產品目錄頁面: 1275 (CN2011-ZH PDF)
其它名稱: LMK04001BISQEDKR
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Table 23. PLL2 Internal Loop Filter Resistor Values, PLL2_R4_LF
PLL2_R4_LF [2:0]
RESISTANCE
b2
b1
b0
0
< 200
Ω
0
1
10 k
Ω
0
1
0
20 k
Ω
0
1
30 k
Ω
1
0
40 k
Ω
1
0
1
Invalid
1
0
Invalid
1
Invalid
Internal loop filter capacitors for C3 and C4 can be set individually according to the following table.
Table 24. PLL2 Internal Loop Filter Capacitor Values
PLL2_C3_C4_LF [3:0]
Loop Filter Capacitance(pF)
b3
b2
b1
b0
0
C3 = 0, C4 = 10
0
1
C3 = 0, C4 = 60
0
1
0
C3 = 50, C4 = 10
0
1
C3 = 0, C4 = 110
0
1
0
C3 = 50, C4 = 110
0
1
0
1
C3 = 100, C4 = 110
0
1
0
C3 = 0, C4 = 160
0
1
C3 = 50, C4 = 160
1
0
C3 = 100, C4 = 10
1
0
1
C3 = 100, C4 = 60
1
0
1
0
C3 = 150, C4 = 110
1
0
1
C3 = 150, C4 = 60
1
0
Reserved
1
0
1
Reserved
1
0
Reserved
1
Reserved
PLL1 CP TRI-STATE and PLL2 CP TRI-STATE
The charge pump output of either CPout1 or CPout2 may be placed in a TRI-STATE mode by setting the
appropriate PLLx CP TRI-STATE bit.
Table 25. PLL1 Charge Pump TRI-STATE bit values
PLL1 CP TRI-STATE
Description
1
PLL1 CPout1 is at TRI-STATE
0
PLL1 CPout1 is active
Table 26. PLL2 Charge Pump TRI-STATE bit values
PLL2 CP TRI-STATE
Description
1
PLL2 CPout2 is at TRI-STATE
0
PLL2 CPout2 is active
Copyright 2008–2011, Texas Instruments Incorporated
39
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