參數(shù)資料
型號(hào): LM98725
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 模擬信號(hào)調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO56
封裝: TSSOP-56
文件頁(yè)數(shù): 1/14頁(yè)
文件大小: 464K
代理商: LM98725
LM98725
September 24, 2009
3 Channel, 16-Bit, 81 MSPS Analog Front End with LVDS/
CMOS Output, Integrated CCD/CIS Sensor Timing
Generator and Spread Spectrum Clock Generation
General Description
The LM98725 is a fully integrated, high performance 16-Bit,
81 MSPS signal processing solution for digital color copiers,
scanners, and other image processing applications. High-
speed signal throughput is achieved with an innovative archi-
tecture utilizing Correlated Double Sampling (CDS), typically
employed with CCD arrays, or Sample and Hold (S/H) inputs
(for higher speed CCD or CMOS image sensors). The signal
paths utilize 8 bit Programmable Gain Amplifiers (PGA), a
+/-9-Bit offset correction DAC and independently controlled
Digital Black Level correction loops for each input. The PGA
and offset DAC are programmed independently allowing
unique values of gain and offset for each of the three analog
inputs. The signals are then routed to a 81MHz high perfor-
mance analog-to-digital converter (ADC). The fully differential
processing channel shows exceptional noise immunity, hav-
ing a very low noise floor of -74dB. The 16-bit ADC has
excellent dynamic performance making the LM98725 trans-
parent in the image reproduction chain.
A very flexible integrated Spread Spectrum Clock Generation
(SSCG) modulator is included to assist with EM compliance
and reduce system costs.
Applications
Multi-Function Peripherals
High-speed Currency/Check Scanners
Flatbed or Handheld Color Scanners
High-speed Document Scanners
Features
LVDS/CMOS Outputs
LVDS/CMOS/Crystal Clock Source with PLL Multiplication
Integrated Flexible Spread Spectrum Clock Generation
CDS or S/H Processing for CCD or CIS sensors
Independent Gain/Offset Correction for Each Channel
Automatic per-Channel Gain and Offset Calibration
Programmable Input Clamp Voltage
Flexible CCD/CIS Sensor Timing Generator
Key Specifications
Maximum Input Level
1.2 or 2.4 Volt Modes
(both with + or - polarity option)
ADC Resolution
16-Bit
ADC Sampling Rate
81 MSPS
INL
+17/- 28 LSB (typ)
Channel Sampling Rate
30/30/27 MSPS
PGA Gain Steps
256 Steps
PGA Gain Range
0.62 to 8.3x
Analog DAC Resolution
+/-9 Bits
Analog DAC Range
+/-307mV or +/-614mV
Digital DAC Resolution
+/-6 Bits
Digital DAC Range
-2048 LSB to + 2016 LSB
SNR
-74dB (@0dB PGA Gain)
Power Dissipation
755mW (LVDS)
Operating Temp
0 to 70°C
Supply Voltage
3.3V Nominal (3.0V to 3.6V range)
System Block Diagram
30085370
2009 National Semiconductor Corporation
300853
www.national.com
LM98725
3
Channel,
16-Bit,
81
MSPS
Analog
Front
End
with
LVDS/CMOS
Output
Integrated
Sensor
Timing
Generator
and
Spread
Spectrum
Clock
Generation
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