參數(shù)資料
型號: LM9812
廠商: National Semiconductor Corporation
英文描述: LM9812 30-Bit Color Linear CCD Sensor Processor
中文描述: LM9812 30位彩色線陣CCD傳感器處理器
文件頁數(shù): 21/37頁
文件大小: 479K
代理商: LM9812
21
http://www.national.com
Red PGA
(3)
Green PGA
(4)
Blue PGA
(5)
D7
0
0
0
0
0
0
D4
(MSB)
0
0
0
1
1
1
D3
0
0
0
1
1
1
D2
0
0
0
1
1
1
D1
0
0
1
0
1
1
D0
(LSB)
0
1
0
1
0
1
Typical Gain
(V/V)
0.93
1.00
3.00
Coarse Color
Balance PGA
(Blue with x3
multiplier bit set)
(5)
D7
1
1
1
1
1
1
D4
(MSB)
0
0
0
1
1
1
D3
0
0
0
1
1
1
D2
0
0
0
1
1
1
D1
0
0
1
0
1
1
D0
(LSB)
0
1
0
1
0
1
Typical Gain
(V/V)
2.79
3.00
9.00
Internal
Offset
Subtractor
Coefficient
(6)
D7
(MSB)
0
0
0
1
1
1
D6
0
0
0
1
1
1
D5
0
0
0
1
1
1
D4
0
0
0
1
1
1
D3
0
0
0
1
1
1
D2
0
0
0
1
1
1
D1
0
0
1
0
1
1
D0
(LSB)
0
1
0
1
0
1
Offset
(in ADC LSBs)
0
1
2
253
254
255
Internal
Multiplier
Gain
Coefficient
(7, 8)
D9
(MSB)
0
0
0
1
1
1
D8
0
0
0
1
1
1
D7
0
0
0
1
1
1
D2
0
0
0
1
1
1
D1
0
0
1
0
1
1
D0
(LSB)
0
1
0
1
0
1
Gain
(V/V)
See
Equation 5
Internal/External
Coefficient
Clocks (9)
D7
0
1
External Coefficient Clock Source
Internal Coefficient Clock Source
Number of
Coefficient
Clocks (9)
D5
0
1
GCLK and OCLK
GCLK only
Number of
Databuses in
System (9)
D4
0
1
2 Databuses
1 Databus
Table 2: Configuration Register Parameters
(Continued)
Note:
t
MCLK
= 1/f
MCLK
= 1 MCLK period. Examples given in parenthesis are for f
MCLK
= 24MHz (t
MCLK
= 41.66ns).
Parameter
(Address)
Control Bits
Result
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