參數(shù)資料
型號(hào): LM96194CISQ
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 電源管理
英文描述: TruTherm⑩ Hardware Monitor with PI Fan Control for Workstation Management
中文描述: 9-CHANNEL POWER SUPPLY SUPPORT CKT, QCC48
封裝: LLP-48
文件頁數(shù): 19/24頁
文件大?。?/td> 303K
代理商: LM96194CISQ
AC Electrical Characteristics
The following limits apply for +3.0 V
DC
to +3.6 V
DC
, unless otherwise noted.
Bold face limits apply for T
A
= T
J
= T
MIN
to T
MAX
of
the operating range;
all other limits T
A
= T
J
= 25°C unless otherwise noted.
Symbol
Parameter
Conditions
Typical
(Note 9)
Limits
(Note 10)
Units
(Limits)
FAN RPM-TO-DIGITAL CHARACTERISTICS
Counter Resolution
Number of fan tach pulses count is based
on
Counter Frequency
Accuracy
PWM OUTPUT CHARACTERISTICS
Frequency Tolerances
Duty-Cycle Tolerance
RESET INPUT/OUTPUT CHARACTERISTICS
Output Pulse Width
Upon Power Up
Minimum Input Pulse Width
Reset Output Fall Time
SMBus TIMING CHARACTERISTICS
f
SMBCLK
SMBCLK (Clock) Clock Frequency
14
2
bits
pulses
22.5
kHz
±6
% (max)
% (max)
% (max)
ms (min)
ms (max)
μs (min)
μs (max)
kHz (min)
kHz (max)
±6
±6
±2
250
330
10
1
1.6V to 0.4V Logic Levels
10
100
t
BUF
SMBus Free Time between Stop and
Start Conditions
Hold time after (Repeated) Start
Condition. After this period, the first clock
is generated.
Repeated Start Condition Setup Time
4.7
μs (min)
t
HD;STA
4.0
μs (min)
t
SU;STA
t
SU;STO
t
SU;DAT
t
HD;DAT
4.7
4.0
μs (min)
Stop Condition Setup Time
μs (min)
Data Input Setup Time to SMBCLK High
250
300
1075
4.7
50
4.0
50
1
300
25
35
ns (min)
ns (min)
ns (max)
μs (min)
μs (max)
μs (min)
μs (max)
μs (max)
Data Output Hold Time after SMBCLK
Low
SMBCLK Low Period
t
LOW
t
HIGH
SMBCLK High Period
t
R
t
F
t
TIMEOUT
Rise Time
Fall Time
ns (max)
Timeout
SMBDAT or SMBCLK low
time required to
reset the Serial Bus
Interface to the Idle State
Time in which a device must be
operational after power-on reset
Capacitance Load on SMBCLK and
SMBDAT
31
ms
ms (min)
ms (max)
t
POR
V
DD
> +2.8V
500
ms (max)
C
L
400
pF (max)
19
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