3.0 Applications Hints
(Continued)
AMD Sempron
1.00261
0.93
3.1.3 Compensating for Different Non-Ideality
In order to compensate for the errors introduced by non-
ideality, the temperature sensor is calibrated for a particular
processor. National Semiconductor temperature sensors are
always calibrated to the typical non-ideality and series resis-
tance of a given processor type. The LM95241 is calibrated
for two non-ideality factors and series resistance values thus
supporting the MMBT3904 transistor and the Intel processor
on 65nm or 90nm process without the requirement for addi-
tional trims. For most accurate measurements TruTherm
mode should be turned on when measuring the Intel proces-
sor on the 65nm or 90nm process to minimize the error
introduced by the false non-ideality spread (see
Section
3.1.1 Diode Non-Ideality Factor Effect on Accuracy
). When a
temperature sensor calibrated for a particular processor type
is used with a different processor type, additional errors are
introduced.
Temperature errors associated with non-ideality of different
processor types may be reduced in a specific temperature
range of concern through use of software calibration. Typical
Non-ideality specification differences cause a gain variation
of the transfer function, therefore the center of the tempera-
ture range of interest should be the target temperature for
calibration purposes. The following equation can be used to
calculate the temperature correction factor (T
) required to
compensate for a target non-ideality differing from that sup-
ported by the LM95241.
T
CF
= [(
η
S
η
Processor
) ÷
η
S
] x (T
CR
+ 273 K)
where
η
S
= LM95241 non-ideality for accuracy specification
η
T
= target thermal diode typical non-ideality
T
CR
= center of the temperature range of interest in C
The correction factor of
Equation (7)
should be directly
added to the temperature reading produced by the
LM95233. For example when using the LM95241, with the
3904 mode selected, to measure a AMD Athlon processor,
with a typical non-ideality of 1.008, for a temperature range
of 60 C to 100 C the correction factor would calculate to:
T
CF
=[(1.0031.008)÷1.003]x(80+273) =1.75C
Therefore, 1.75C should be subtracted from the tempera-
ture readings of the LM95241 to compensate for the differing
typical non-ideality target.
(7)
3.2 PCB LAYOUT FOR MINIMIZING NOISE
In a noisy environment, such as a processor mother board,
layout considerations are very critical. Noise induced on
traces running between the remote temperature diode sen-
sor and the LM95241 can cause temperature conversion
errors. Keep in mind that the signal level the LM95241 is
trying to measure is in microvolts. The following guidelines
should be followed:
1.
V
should be bypassed with a 0.1μF capacitor in par-
allel with 100pF. The 100pF capacitor should be placed
as close as possible to the power supply pin. A bulk
capacitance of approximately 10μF needs to be in the
near vicinity of the LM95241.
2.
A 100pF diode bypass capacitor is recommended to
filter high frequency noise but may not be necessary.
Make sure the traces to the 100pF capacitor are
matched. Place the filter capacitors close to the
LM95241 pins.
3.
Ideally, the LM95241 should be placed within 10cm of
the Processor diode pins with the traces being as
straight, short and identical as possible. Trace resis-
tance of 1
can cause as much as 1C of error. This
error can be compensated by using simple software
offset compensation.
4.
Diode traces should be surrounded by a GND guard ring
to either side, above and below if possible. This GND
guard should not be between the D+ and D lines. In the
event that noise does couple to the diode lines it would
be ideal if it is coupled common mode. That is equally to
the D+ and D lines.
5.
Avoid routing diode traces in close proximity to power
supply switching or filtering inductors.
6.
Avoid running diode traces close to or parallel to high
speed digital and bus lines. Diode traces should be kept
at least 2cm apart from the high speed digital traces.
7.
If it is necessary to cross high speed digital traces, the
diode traces and the high speed digital traces should
cross at a 90 degree angle.
8.
The ideal place to connect the LM95241’s GND pin is as
close as possible to the Processor’s GND that is asso-
ciated with the sense diode.
9.
Leakage current between D+ and GND and between D+
and D should be kept to a minimum. Thirteen nano-
amperes of leakage can cause as much as 0.2C of
error in the diode temperature reading. Keeping the
printed circuit board as clean as possible will minimize
leakage current.
Noise coupling into the digital lines greater than 400mVp-p
(typical hysteresis) and undershoot less than 500mV below
GND, may prevent successful SMBus communication with
the LM95241. SMBus no acknowledge is the most common
symptom, causing unnecessary traffic on the bus. Although
the SMBus maximum frequency of communication is rather
low (100kHz max), care still needs to be taken to ensure
proper termination within a system with multiple parts on the
bus and long printed circuit board traces. An RC lowpass
filter with a 3db corner frequency of about 40MHz is included
on the LM95241’s SMBCLK input. Additional resistance can
be added in series with the SMBDAT and SMBCLK lines to
further help filter noise and ringing. Minimize noise coupling
by keeping digital traces out of switching power supply areas
as well as ensuring that digital lines containing high speed
data communications cross at right angles to the SMBDAT
and SMBCLK lines.
20199717
FIGURE 4. Ideal Diode Trace Layout
L
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