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| 型號： | LM92CIMX/NOPB |
| 廠商： | National Semiconductor |
| 文件頁數(shù)： | 6/25頁 |
| 文件大小： | 1472K |
| 描述： | IC SENSOR TEMP/THERM COMP 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 系列： | PowerWise® |
| 功能： | 溫度監(jiān)控系統(tǒng)（傳感器） |
| 傳感器類型： | 內(nèi)部 |
| 感應(yīng)溫度： | -55°C ~ 150°C |
| 精確度： | ±1.5°C（最小值） |
| 拓?fù)洌?/td> | ADC，比較器，寄存器庫 |
| 輸出類型： | 2 線串行，I²C? |
| 輸出警報： | 是 |
| 輸出風(fēng)扇： | 無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -55°C ~ 150°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | *LM92CIMX *LM92CIMX/NOPB LM92CIMX LM92CIMX-ND LM92CIMX/NOPBTR |
LM 92
SNIS110D MARCH 2000REVISED MARCH 2013
www.ti.com
Digital DC Characteristics (continued)
Unless otherwise noted, these specifications apply for +V
S
= +2.7V to +5.5V for LM92CIM . Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= +25 癈, unless otherwise noted.
Typical
(1)
Limits
(2)
Unit
Symbol
Parameter
Conditions
(Limit)
T_CRIT_A Output Saturation Voltage I
OUT
= 4.0 mA
0.8
V (max)
(3)
T_CRIT_A Delay
1
Conversions
(max)
t
OF
Output Fall Time
C
L
= 400 pF
250
ns (max)
I
O
= 3 mA
(3) For best accuracy, minimize output loading. 10k pull-ups resistors should be sufficient. Higher sink currents can affect sensor accuracy
with internal heating. This can cause an error of 0.64 癈 at full rated sink current and saturation voltage based on junction-to-ambient
thermal resistance.
Serial Bus Digital Switching Characteristics
Unless otherwise noted, these specifications apply for +V
S
= +2.7V to +5.5V for LM92CIM . Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= +25 癈, unless otherwise noted. CL (load capacitance) on output lines = 80 pF unless
otherwise specified. Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits T
A
= T
J
= +25 癈, unless otherwise noted.
Typical
(1)
Limits
(2) (3)
Unit
Symbol
Parameter
Conditions
(Limit)
t
1
SCL (Clock) Period
2.5
祍(min)
1
ms(max)
t
2
Data in Set-Up Time to SCL High
100
ns(min)
t
3
Data Out Stable after SCL Low
0
ns(min)
t
4
SDA Low Set-Up Time to SCL Low (Start Condition)
100
ns(min)
t
5
SDA High Hold Time after SCL High (Stop Condition)
100
ns(min)
t
TIMEOUT
SDA and SCL Time Low for Reset of Serial Interface
(4)
75
ms (min)
300
ms (max)
(1) Typical values are at T
A
= 25 癈 and represent most likely parametric norm.
(2) Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).
(3) Timing specifications are tested at the bus input logic levels (Vin(0)=0.3xVA for a falling edge and Vin(1)=0.7xVA for a rising edge) when
the SCL and SDA edge rates are similar.
(4) Holding the SDA and/or SCL lines Low for a time interval greater than t
TIMEOUT
will cause the LM92 to reset SCL and SDA to the IDLE
state of the serial bus communication (SDA and SCL set High).
Figure 4. Serial Bus Communication
6
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Copyright ?20002013, Texas Instruments Incorporated
Product Folder Links: LM92
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