參數(shù)資料
型號: LM9073S
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 基準(zhǔn)電壓源/電流源
英文描述: Dual High Current Low-Dropout System Regulator
中文描述: DUAL OUTPUT, FIXED POSITIVE LDO REGULATOR, PSSO11
封裝: TO-263, 11 PIN
文件頁數(shù): 10/18頁
文件大?。?/td> 718K
代理商: LM9073S
Application Information
(Continued)
ranging up to 700mA. This relatively high level of output cur-
rent is sufficient to provide power to a large number of load
circuits in a variety of module applications.
This output has a short to ground current limit between
900mA and 2A. It is not protected for shorts to battery how-
ever, but can withstand an output short to a potential of 7
Volts or less.
To maintain stability of this supply line an output bypass ca-
pacitor is required. This capacitor must be at least 6μF with
an equivalent series resistance (ESR) between 0.3
and 3
over temperature.
The Main Output is sensed for the generation of the system
reset output.
External Supply Output (pin 5)
The External Supply Output regulator is a secondary 5V, 2%
tolerance regulated output of the LM9073. this 100mAoutput
is available to bias sensors and other devices located exter-
nal to the main system module.
For providing remote power the External Supply Output is
fully protected against short circuit connections to the battery
or input supply (up to 27V) and to ground. These shorted
fault conditions do not effect the operation of the main supply
nor generate a reset of the system.
Like the main output a bypass capacitor is required for stabil-
ity. This capacitor should be also greater than 6μF with an
ESR between 0.3
and 3
.
Reset Output (pin 7)
The Reset Output is an active low logic signal provided to re-
set a system mircocontroller on power up and in the event
that the Main Output falls out of regulation. This output is
guaranteed to provide a logic low level (
<
0.4V) whenever
the Main Output supply is below a threshold set by the Reset
Adjust pin strap option (see ResetAdjust section) or is pulled
above 5.75V. This general reset prevents erratic system op-
eration which may occur with out-of-specification supply po-
tentials.
The Reset Output has an active pull down which can sink up
to 15mA of current and a passive pull-up (through a 4K
re-
sistor) to the Main Output to ensure voltage compatibility
with the system supply. Capacitive loading on this reset line
will directly affect the rise time of the reset signal. The Reset
Output will maintain a logic low level with a Main Output volt-
age of only 1V. Below 1V the active pull-down device
switches OFF (sink current of only 500μA). At such a low
supply potential, system controllers are generally inopera-
tive.
The Reset Output has a built-in delay time interval which is
programmable by the section of the delay capacitor.
Reset Adjust (pin 11)
The low Vmain threshold voltage for generating a system re-
set can be shifted by 500mV through the use of a pin strap to
ground on pin 11. With this pin shorted to ground the thresh-
old is between 4.5V and 4.7V. With this pin left open the
threshold is shifted to between 4.0V and 4.2V. This lower
threshold allows the system to remain operational longer
during power down. The higher threshold ensures that the
system is reset when the nominal 5V supply is low by 10%,
which in some cases can produce uncertain microprocessor
operation.
Delay Capacitor (pin 8)
Figure 2. Reset Generator and Watchdog Circuitry
DS101296-17
L
www.national.com
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