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參數資料
| 型號： | LM75BIMX-5+ |
| 廠商： | Maxim Integrated |
| 文件頁數： | 10/12頁 |
| 文件大?。?/td> | 701K |
| 描述： | IC TEMP SENSOR WATCHDOG 8SOIC |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 100 |
| 功能： | 溫度監(jiān)視系統(tǒng)（傳感器），監(jiān)視器 |
| 傳感器類型： | 內部 |
| 感應溫度： | -55°C ~ 125°C |
| 精確度： | ±3°C（最小值） |
| 拓撲： | ADC（三角積分型），比較器，寄存器庫 |
| 輸出類型： | 2 線串行，I²C? |
| 輸出警報： | 是 |
| 輸出風扇： | 是 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
Configuration Register
The 8-bit Configuration register sets the fault queue, OS
polarity, shutdown control, and whether the OS output
functions in comparator or interrupt mode. When writing
to the Configuration register, set bits D7, D6, and D5 to
zero (see Table 5).
Bits D4 and D3, the fault queue bits, determine the
number of faults necessary to trigger an OS condition
(see Table 6). The number of faults set in the queue
must occur consecutively to trip the OS output. The
fault queue prevents OS false tripping in noisy environ-
ments.
Set bit D2, the OS polarity bit, to zero to force the OS
output polarity to active low. Set bit D2 to 1 to set the
OS output polarity to active high. OS is an open-drain
output under all conditions and requires a pullup resis-
tor to output a high voltage (see Figure 1).
Set bit D1, the comparator/interrupt bit to zero to oper-
ate OS in comparator mode. In comparator mode, OS
is asserted when the temperature rises above the T
OS
value. OS is deasserted when the temperature drops
below the T
HYST
value (see Figure 1). Set bit D1 to 1 to
operate OS in interrupt mode. OS is asserted in inter-
rupt mode when the temperature rises above the T
OS
value or falls below the T
HYST
value. OS is deasserted
only after performing a read operation.
Set bit D0, the shutdown bit, to zero for normal opera-
tion. Set bit D0 to 1 to shutdown the LM75s internal
blocks. The I
2
C interface remains active as long as the
shutdown bit is set. The T
OS
, T
HYST
, and Configuration
registers can still be written to and read from while in
shutdown.
Applications Information
LM75 measures the temperature of its own die. The
thermal path between the die and the outside world
determines the accuracy of temperature measure-
ments. Most of the heat flows in to or out of the die
through the leads. Because of this, the LM75 most easi-
ly measures the PCB temperature. For ambient temper-
ature measurements, mount the LM75 on a separate
PCB away from high power sources. Temperature
errors due to self heating of the LM75 die is minimal
due to the low supply current.
Digital Noise Issues
The lowpass filters in the SCL and SDA digital lines miti-
gate the effects of bus noise, and make communica-
tions in noisy environments more robust. Good layout
practices also help. Keep switching power supplies
away from digital lines, and arrange for high-speed dig-
ital traces to cross SCL and SDA at right angles.
Properly terminate long PCB traces and bus traces
connected to multiple slaves.
Serial bus no-acknowledge (which causes unnecessary
bus traffic) is the most common symptom of excessive
noise coupling into the SDA and SCL lines. Noise with
amplitude greater than the LM75s hysteresis (400mV
P-P
,
typ), overshoot greater than 300mV above +V
S
, and
undershoot more than 300mV below GND may prevent
successful serial communication.
Resistance can be added in series with the SDA and
SCL lines to help filter noise and ringing. A 5k?resistor
placed in series with the SCL line and as close as pos-
sible to the SCL pin, with the 5pF to 10pF stray capaci-
tance of the device, provides a 6MHz to 12MHz
lowpass filter, which is sufficient filtering in many cases.
Digital Temperature Sensor and Thermal
Watchdog with 2-Wire Interface
10 ______________________________________________________________________________________
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
Fault Queue
Fault Queue
OS Polarity
Comparator/
Interrupt
Shutdown
Table 5. Configuration Register Definition
D4
D3
NUMBER OF FAULTS
0
0
1 (POR state)
0
1
2
1
0
4
1
1
6
Table 6. Configuration Register Fault
Queue Bits
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