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參數(shù)資料
| 型號(hào)： | LM555CS |
| 英文描述： | Analog Timer Circuit |
| 中文描述： | 模擬定時(shí)器電路 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 79K |
| 代理商： | LM555CS |
8-5
Schematic Diagram
Typical Applications
Reset Timer (Monostable Operation)
Figure 1 shows the CA555 connected as a reset timer. In this
mode of operation capacitor CT is initially held discharged by
a transistor on the integrated circuit. Upon closing the “start”
switch, or applying a negative trigger pulse to terminal 2, the
integral timer ip-op is “set” and releases the short circuit
across CT which drives the output voltage “high” (relay ener-
gized). The action allows the voltage across the capacitor to
increase exponentially with the constant t = R1CT. When the
voltage across the capacitor equals 2/3 V+, the comparator
resets the ip-op which in turn discharges the capacitor rap-
idly and drives the output to its low state.
Output Rise Time
tR
-
100
-
100
-
ns
Output Fall Time
tF
-
100
-
100
-
ns
NOTES:
2. When the output is in a high state, the DC supply current is typically 1mA less than the low state value.
3. The threshold current will determine the sum of the values of R1 and R2 to be used in Figure 4 (astable operation); the maximum total
R1 + R2 = 20M.
Electrical Specications
TA = 25
oC, V+ = 5V to 15V Unless Otherwise Specied (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
CA555, LM555
CA555C, LM555C, NE555
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
6
THRESHOLD
7
RESET
DISCHARGE
V-
RESET
DISCHARGE
3
OUTPUT
FLIP-FLOP
TRIGGER
COMPARATOR
THRESHOLD
COMPARATOR
4.7K
830
4.7K
D2
D1
Q3
Q4
Q7
Q5
Q2
Q1
10K
Q8
Q6
100
100K
Q9
Q11 Q12
1K
Q10
5K
Q13
Q16
7K
D3
Q14
Q15
Q17
3.9K
Q19
Q20
Q21
Q18
8
V+
CONTROL
VOLTAGE
5K
6.8K
5K
4.7K
220
4.7K
5
2
4
1
TRIGGER
D4
NOTE: Resistance values are in ohms.
CA555, CA555C, LM555, LM555C, NE555
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