參數(shù)資料
型號: LM5110-1MX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 外設及接口
英文描述: MC 1,5/16-ST-3,5
中文描述: 5 A 2 CHANNEL, BUF OR INV BASED PRPHL DRVR, PDSO8
封裝: MS-012AA, SOIC-8
文件頁數(shù): 8/13頁
文件大?。?/td> 269K
代理商: LM5110-1MX
Typical Performance Characteristics
(Continued)
Delay Time vs Temperature
RDSON vs Supply Voltage
20079216
20079217
UVLO Thresholds and Hysteresis vs Temperature
20079218
Detailed Operating Description
LM5110 dual gate driver consists of two independent and
identical driver channels with TTL compatible logic inputs
and high current totem-pole outputs that source or sink
current to drive MOSFET gates. The driver output consist of
a compound structure with MOS and bipolar transistor oper-
ating in parallel to optimize current capability over a wide
output voltage and operating temperature range. The bipolar
device provides high peak current at the critical threshold
region of the MOSFET VGS while the MOS devices provide
rail-to-rail output swing. The totem pole output drives the
MOSFET gate between the gate drive supply voltage V
CC
and the power ground potential at the V
EE
pin.
The control inputs of the drivers are high impedance CMOS
buffers with TTL compatible threshold voltages. The nega-
tive supply of the input buffer is connected to the input
ground pin IN_REF. An internal level shifting circuit connects
the logic input buffers to the totem pole output drivers. The
level shift circuit and separate input/output ground pins pro-
vide the option of single supply or split supply configurations.
When driving MOSFET gates from a single positive supply,
the IN_REF and V
EE
pins are both connected to the power
ground. The LM5110 pinout was designed for compatibility
with industry standard gate drivers in single supply gate
driver applications. Pin 1 (IN_REF) on the LM5110 is a
no-connect on standard driver IC’s. Connecting pin 1 to pin 3
(V
EE
) on the printed circuit board accommodates the pin-out
of both the LM5110 and competitive drivers.
The isolated input/output grounds provide the capability to
drive the MOSFET to a negative VGS voltage for a more
robust and reliable off state. In split supply configuration, the
IN_REF pin is connected to the ground of the controller
which drives the LM5110 inputs. The V
EE
pin is connected to
a negative bias supply that can range from the IN-REF as
much as 14V below the V
gate drive supply. The maxi-
mum recommended voltage difference between V
and
IN_REF or between V
and V
is 14V. The minimum
voltage difference between V
CC
and IN_REF is 3.5V.
Enhancement mode MOSFETs do not inherently require a
negative bias on the gate to turn off the FET. However,
certain applications may benefit from the capability of nega-
tive VGS voltage during turn-off including:
1.
when the gate voltages cannot be held safely below the
threshold voltage due to transients or coupling in the
printed circuit board.
L
www.national.com
8
相關PDF資料
PDF描述
LM5110-1SD MC 1,5/17-ST-3,5
LM5110-1SDX MC 1,5/18-ST-3,5
LM5110-1M Dual 5A Compound Gate Driver with Negative Output Voltage Capability
LM5110-3MX Dual 5A Compound Gate Driver with Negative Output Voltage Capability
LM5110-3SD Dual 5A Compound Gate Driver with Negative Output Voltage Capability
相關代理商/技術參數(shù)
參數(shù)描述
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LM5110-1MX/S7002316 制造商:Texas Instruments 功能描述:
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