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參數(shù)資料
| 型號(hào)： | LM5070 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Integrated Power Over Ethernet PD Interface and PWM Controller |
| 中文描述： | 集成以太網(wǎng)供電PD接口和PWM控制器 |
| 文件頁(yè)數(shù)： | 3/17頁(yè) |
| 文件大?。?/td> | 833K |
| 代理商： | LM5070 |
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Pin Description
PIN
1
NAME
V
IN
DESCRIPTION
APPLICATION INFORMATION
System high potential input.
The diode “OR” of several lines entering the PD, it is the more
positive input potential.
Connect a 25k
signature resistor from V
IN
to this pin for signature
detection.
Connect the classification programming resistor from this pin to
V
EE
.
An external resistor divider from V
IN
to UVLORTN programs the
shutdown levels with a 2.00V threshold at the UVLO pin.
Hysteresis is set by a switched internal 10uA current source that
forces additional current into the resistor divider.
Connect the bottom resistor of the resistor divider between the
UVLO pin and this pin.
Programs the inrush current limit for the device. If left open, the
inrush current limit will default to 400mA max.
Diode “OR’d” to the RJ45 connector and PSE’s –48V supply, it is
the more negative input potential.
The drain of the internal current limiting power MOSFET which
connects V
EE
to the return path of the dc-dc converter.
DC-DC converter gate driver output with 800mA peak sink current
capability.
When the auxiliary transformer winding (if used) raises the voltage
on this pin above the regulation set point, the internal series pass
regulator will shutdown, reducing the controller power dissipation.
Inverting input of the internal error amplifier. The non-inverting
input is internally connected to a 1.25V reference.
COMP pull-up is provided by an internal 5K resistor which may be
used to bias an opto-coupler transistor.
Current sense input for current mode control and over-current
protection. Current limiting is accomplished using a dedicated
current sense comparator. If the CS pin voltage exceeds 0.5V the
OUT pin switches low for cycle-by-cycle current limiting. CS is held
low for 50ns after OUT switches high to blank leading edge current
spikes.
An external resistor connected from RT to ARTN sets the oscillator
frequency. This pin will also accept narrow ac-coupled
synchronization pulses from an external clock.
An external capacitor and an internal 10uA current source set the
soft-start ramp rate.
RTN for sensitive analog circuitry including the SMPS current limit
amplifier.
Internally bonded to the die substrate. Connect to V
EE
potential for
low thermal impedance.
2
RSIG
Signature resistor pin.
3
RCLASS
Classification resistor pin.
4
UVLO
Line under-voltage lockout.
5
UVLORTN
Return for the external UVLO resistors, if
used.
Current limit programming pin.
6
RCLP
7
V
EE
System low potential input.
8
RTN
System return for the PWM converter.
9
OUT
Output of the PWM controller.
10
V
CC
Output of the internal high voltage series
pass regulator. Regulated output voltage
is nominally 7.8V.
Feedback signal.
11
FB
12
COMP
The output of the error amplifier and
input to the Pulse Width Modulator.
Current sense input.
13
CS
14
RT / SYNC Oscillator timing resistor pin and
synchronization input.
15
SS
Soft-start input.
16
ARTN
Analog PWM supply return.
—
EP
Exposed PAD, underside of the LLP
package option.
L
www.national.com
3
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