Application Information
(Continued)
Bypass Capacitor Value Selection
Besides optimizing the input capacitor value, careful consid-
eration should be paid to value of C
B
, the capacitor con-
nected between the BYPASS pin and ground. Since C
B
determines how fast the LM4874 settles to its quiescent
operating state, its value is critical when minimizing turn-on
transients. The slower the LM4874’s outputs ramp to their
quiescent DC voltage (nominally
1
2
V
), the smaller the
turn-on transient. Choosing C
equal to 0.47μF along with a
small value of C
(in the range of 0.047μF to 0.47μF), pro-
duces a transient-free turn-on and shutdown function. As
discussed above, choosing C
no larger than necessary for
the desired bandwidth helps minimize turn-on transients.
OPTIMIZING OUTPUT TRANSIENT REDUCTION (CLICK
AND POP PERFORMANCE)
The LM4874 contains circuitry to minimize turn-on and shut-
down transients or ’clicks and pop’. For this discussion,
turn-on refers to either applying the power supply voltage or
when the shutdown mode is deactivated. While the power
supply voltage is ramping to its final value, the LM4874’s
internal amplifiers are configured as unity gain buffers. An
internal current source changes the voltage of the BYPASS
pin in a controlled, linear manner. Ideally, the amplifier inputs
and outputs track the voltage applied to the BYPASS pin.
The gain of the internal amplifiers remains unity until the
voltage on the bypass pin reaches 1/2 V
DD
. As soon as the
voltage on the BYPASS pin is stable, the device becomes
fully operational. Although the bypass pin current can not be
modified, changing the size of C
B
alters the device’s turn-on
time and the magnitude of output transients. Increasing the
value of C
reduces the magnitude of turn-on transients.
However, this presents a tradeoff: as the size of C
in-
creases, the turn-on time increases. There is a linear rela-
tionships between the size of C
+ 2(C
) and the turn-on
time. The table shows some typical turn-on times for various
values of C
B
:
C
B
Ton
C
i
= 0.47μF
110ms
120ms
140ms
170ms
240ms
C
i
= 0.33μF
80ms
90ms
100ms
140ms
210ms
0.01μF
0.1μF
0.22μF
0.47μF
1.0μF
In order to eliminate ’clicks and pops’, all capacitors must be
discharged before turn-on. Rapidly switching V
may not
allow the capacitors to fully discharge, which may cause
’clicks and pops’.
AUDIO POWER AMPLIFIER DESIGN
Audio Amplifier Design: Driving 1W into an 8
Load
The following are the desired operational parameters:
Power Output:
Load Impedance:
Input Level:
Input Impedance:
Bandwidth:
1 W
RMS
8
1 V
RMS
20 k
100 Hz20 kHz
±
0.25 dB
The design begins by specifying the minimum supply voltage
necessary to obtain the desired output power. One way to
find the minimum supply voltage is to use the Output Power
vs Supply Voltage curve in the
Typical Performance Char-
acteristics
section. Another way, using Equation (6), is to
calculate the peak output voltage necessary to achieve the
desired output power for a given load impedance. To ac-
count for the amplifier’s dropout voltage, two additional volt-
ages, based on the Dropout Voltage vs Supply Voltage in the
Typical Performance Characteristics
curves, must be
added to the result obtained by Equation (6). The result is
Equation (7).
(6)
V
DD
≥
(V
OUTPEAK
+ (V
OD
TOP
+ V
OD
BOT
))
(7)
The Output Power vs Supply Voltage graph for an 8
load
indicates a minimum supply voltage of 4.6V. This is easily
met by the commonly used 5V supply voltage. The additional
voltage creates the benefit of headroom, allowing the
LM4874 to produce peak output power in excess of 1W
without clipping or other audible distortion. The choice of
supply voltage must also not create a situation that violates
of maximum power dissipation as explained above in the
Power Dissipation
section.
After satisfying the LM4874’s power dissipation require-
ments, the minimum differential gain is found using Equation
(8).
(8)
Thus, a minimum gain of 2.83 allows the LM4874’s to reach
full output swing and maintain low noise and THD+N perfor-
mance. For this example, letA
VD
= 3. In the example design,
the gain will be set to 10dB (A
= 3.2) by applying a logic
low to GAIN 0 and a logic high to GAIN 1.
The last step in this design example is setting the amplifier’s
-3dB frequency bandwidth. To achieve the desired
±
0.25dB
pass band magnitude variation limit, the low frequency re-
sponse must extend to at least one-fifth the lower bandwidth
limit and the high frequency response must extend to at least
five times the upper bandwidth limit. This extended bandwith
produces a gain variation of -0.17dB at the bandwith’s limits,
well within the
±
0.25dB desired limit. The results are an
f
L
= 100Hz/5 = 20Hz
(9)
and an
f
H
= 20kHz x 5 = 100kHz
(10)
L
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