參數(shù)資料
型號: LM4545
廠商: National Semiconductor Corporation
元件分類: Codec
英文描述: AC ’97 Codec with Stereo Headphone Amplifier and National 3D Sound
中文描述: 交流\u0026#39;97編解碼器與立體聲耳機(jī)放大器和國家3D聲音
文件頁數(shù): 14/16頁
文件大小: 327K
代理商: LM4545
Application Information
(Continued)
Bit
Description
Codec Ready
Bit
Slot 1 data
valid
Slot 2 data
valid
Slot 3 data
valid
Slot 4 data
valid
Comment
15
0=Not Ready, 1=Ready
14
Status Address is valid
13
Status Data is valid
12
Left Audio PCM Data is
valid
Right Audio PCM Data is
valid
11
SD_IN Slot 1: Status Address
The slot echoes the control register which a read was re-
quested on. The address echoed was initiated by a read re-
quest in the previous SD_OUT frame, slot 1.
Bits
19
Description
Reserved
Comment
Stuffed with
0
Echo of Control Register
for which data is being
returned.
Stuffed with
0
’s
18:12
Control
Register Index
11:0
Reserved
SD_IN Slot 2: Status Data
The slot returns the control register data. The data returned
was initiated by a read request in the previous SD_OUT
frame, slot 1.
Bits
Description
Control
Register Read
Data
Reserved
Comment
19:4
3:0
Stuffed with
0
’s
SD_IN Slot 3: PCM Record Left Channel
This slot contains the left ADC sample data. The signal digi-
tized is selected via register 1Ah and subsequently routed
through the Input Mux for recording by the left ADC.
Bits
Description
PCM Record
Left Channel
data
Reserved
Comment
19:2
18 bit audio sample from
left ADC
1:0
Stuffed with
0
’s
SD_IN Slot 4: PCM Record Right Channel
This slot contains the rightADC sample data. The signal digi-
tized is selected via register 1Ah and subsequently routed
through the Input Mux for recording by the right ADC.
Bits
Description
PCM Record
Right Channel
data
Reserved
Comment
19:2
18 bit audio sample from
right ADC
1:0
Stuffed with
0
’s
SD_IN Slots 5-12: Reserved
These SD_IN slots are set to
0
as they are reserved for fu-
ture use.
AC Link Low Power Mode
Reset Register (00h)
Writing any value to this register causes a register reset
which changes all of the registers back to their default val-
ues. If a read is performed on this register, the LM4545 will
return a value of 0D50h implying that National 3D Sound is
implemented, 18bit data is supported for both the ADC’s and
DAC’s and the stereo headphone function is supported.
Master Volume Registers (02h, 04h, 06h)
These registers allows the output levels from LINE_OUT
port, HP_OUT port and MONO_OUT port to be attenuated or
muted. Each step is nominally 1.5dB and each output can be
individually muted by setting the most significant bit to 1.
Mute
0
0
0
1
Default: 8000h
Mx5:Mx0
00 0000
01 1111
1X XXXX
XX XXXX
Function
0dB attenuation
46.5dB attenuation
46.5dB attenuation
mute
PC Beep Register (0Ah)
This register controls the level of the PC_BEEP input. The
PC_BEEP can be both attenuated and muted via register
0Ah. Step size is nominally 3dB. The signal present after the
attenuation and mute block is summed into both the left and
right channels.
Mute
0
0
1
Default: 8000h
PV3:0
0000
1111
XXXX
Function
0dB attenuation
45dB attenuation
mute
Mixer Input Volume Registers (Index 0Ch - 18h)
These registers control the input volume controls including
mute. Each volume control is 5 bit which provides from a
range of +12dB gain to 34.5dB attenuation. For stereo ports,
the left and right levels can be independently set. Muting a
given port is accomplished by setting the MSB to 1. Setting
the MSB to 1 for stereo ports mutes both the left and right
channel. Register 0Eh has an additional 20dB boost for a mi-
crophone level input. This is enabled by setting bit 6 of reg-
ister 0Eh to 1.
DS100069-9
FIGURE 8. AC Link Powerdown Timing
www.national.com
14
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