參數(shù)資料
型號(hào): LM4540VH
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 消費(fèi)家電
英文描述: AC ’97 Codec with National 3D Sound
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, TQFP-48
文件頁(yè)數(shù): 15/16頁(yè)
文件大?。?/td> 298K
代理商: LM4540VH
Application Information
(Continued)
Mixer Input Volume Registers (Index 0Ch - 12h, 18h)
These registers control the input volume controls including
mute. Each volume control is 5 bit which provides from a
range of +12dB gain to 34.5dB attenuation. For stereo ports,
the left and right levels can be independently set. Muting a
given port is accomplished by setting the MSB to 1. Setting
the MSB to 1 for stereo ports mutes both the left and right
channel. Register 0Eh has an additional 20dB boost for a mi-
crophone level input. This is enabled by setting bit 6 of reg-
ister 0Eh to 1.
Mute
0
0
0
1
Default: 8008h (mono regs.), 8808h (stereo regs.)
Gx4:Gx0
00000
01000
01111
XXXXX
Function
+12dB gain
0dB gain
34.5dB attenuation
mute
Record Select Register (1Ah)
This register independently controls the source for the right
and left channel which will be recorded by the stereo ADC.
The default value is 0000h which corresponds to Mic in.
SL2:SL0
0
1
2
3
4
5
6
7
Left Record Source
Mic
CD In (L)
not used
not used
Line In (L)
Stereo Mix (L)
Mono Mix (L)
Phone
SR2:SR0
0
1
2
3
4
5
6
7
Right Record Source
Mic
CD In (R)
not used
not used
Line In (R)
Stereo Mix (R)
Mono Mix (R)
Phone
Record (Input) Gain Register (1Ch)
This registers controls the Record (Input) Gain level for the
stereo input selected via the Record Select Control Register
(1Ah). The gain can be programmed from 0dB to +22.5dB in
1.5dB steps. The level for the left and right channel can be
individually controlled. The input can also be muted by set-
ting the MSB to 1.
Mute
0
0
1
Default: 8000h
Gx3:Gx0
1111
0000
XXXX
Function
22.5dB gain
0dB gain
mute
General Purpose Register (20h)
This register controls many miscellaneous functions imple-
mented on the LM4540. The miscellaneous functions include
POP which allows the PCM to bypass the National 3D
Sound circuitry, 3D which enables or disables the National
3D Sound circuitry, MIX which selects the MONO_OUT
source, MS which selects the microphone mux source, and
LPBK which connects the output of the stereo ADC to the in-
put of the stereo DAC. LPBK provides a digital loopthru path
when enabled.
BIT
Function
POP
PCM out path and mute, 0 = pre 3D, 1 =
post 3D
National 3D Sound on / off 1 = on
Mono output select 0 = Mix, 1 = Mic
Mic select 0 = Mic1 1 = Mic2
ADC/DAC loopback
3D
MIX
MS
LPBK
Powerdown Control / Status Register (26h)
This read/write register is used to monitor subsystem readi-
ness and program LM4540 powerdown states. The lower
half of this register is read only with a
1
indicated the sub-
section is ready. Writing to the lower 8 bits will have no effect.
When the AC Link
Codec Ready
indicator bit (SDATA_IN
slot 0, bit 15) is a 1 it indicates that the AC Link and AC ’97
registers are in a fully operational state. The AC ’97 Control-
ler must further probe the Powerdown Control / Status Reg-
ister to determine exactly which subsections are ready.
BIT
REF
ANL
DAC
ADC
Function
Vref’s up to nominal level
Analog mixers ready
DAC section ready to accept data
ADC section ready to transmit data
The supported powerdown modes are as follows.
BIT
PRO
PR1
PR2
PR3
Function
PCM in ADC’s and Input Mux powerdown
PCM out DAC’s powerdown
Analog Mixer powerdown (VREF still on)
Analog Mixer powerdown (VREF off)
Digital Interface (AC Link) powerdown
(external clk off)
Internal Clk disable
not used
PR4
PR5
PR6
Reserved Registers (28h - 7Ah)
Do not write to these registers as they are reserved.
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