Application Information
(Continued)
Bit
Description
Codec Ready
Bit
Slot 1 data
valid
Slot 2 data
valid
Slot 3 data
valid
Slot 4 data
valid
Comment
15
0=Not Ready, 1=Ready
14
Status Address is valid
13
Status Data is valid
12
Left Audio PCM Data is
valid
Right Audio PCM Data is
valid
11
SD_IN Slot 1: Status Address
The slot echoes the control register which a read was re-
quested on. The address echoed was initiated by a read re-
quest in the previous SD_OUT frame, slot 1.
Bits
19
Description
Reserved
Comment
Stuffed with
″
0
″
Echo of Control Register
for which data is being
returned.
Stuffed with
″
0
″
’s
18:12
Control
Register Index
11:0
Reserved
SD_IN Slot 2: Status Data
The slot returns the control register data. The data returned
was initiated by a read request in the previous SD_OUT
frame, slot 1.
Bits
Description
Control
Register Read
Data
Reserved
Comment
19:4
3:0
Stuffed with
″
0
″
’s
SD_IN Slot 3: PCM Record Left Channel
This slot contains the left ADC sample data. The signal digi-
tized is selected via register 1Ah and subsequently routed
through the Input Mux for recording by the left ADC.
Bits
Description
PCM Record
Left Channel
data
Comment
19:2
18 bit audio sample from
left ADC
Bits
1:0
Description
Reserved
Comment
Stuffed with
″
0
″
’s
SD_IN Slot 4: PCM Record Right Channel
This slot contains the rightADC sample data. The signal digi-
tized is selected via register 1Ah and subsequently routed
through the Input Mux for recording by the right ADC.
Bits
Description
PCM Record
Right Channel
data
Reserved
Comment
19:2
18 bit audio sample from
right ADC
1:0
Stuffed with
″
0
″
’s
SD_IN Slots 5-12: Reserved
These SD_IN slots are set to
″
0
″
as they are reserved for fu-
ture use.
AC Link Low Power Mode
Reset Register (00h)
Writing any value to this register causes a register reset
which changes all of the registers back to their default val-
ues. If this register is read, the codec will return a value of
0D50h indicating that National 3D Sound is implemented
and 18 bit data is supported by both the ADCs and DACs.
Master Volume Registers (02h, 06h)
These registers allows the output levels from LINE_OUT port
and MONO_OUT port to be attenuated or muted. Each step
is nominally 1.5dB and each output can be individually
muted by setting the most significant bit to 1.
Mute
0
0
0
1
Default: 8000h
Mx5:Mx0
00 0000
01 1111
1X XXXX
XX XXXX
Function
0dB attenuation
46.5dB attenuation
46.5dB attenuation
mute
PC Beep Register (0Ah)
This register controls the level of the PC_BEEP input. The
PC_BEEP can be both attenuated and muted via register
0Ah. Step size is nominally 3dB. The signal present after the
attenuation and mute block is summed into both the left and
right channels.
Mute
0
0
1
Default: 8000h
PV3:0
0000
1111
XXXX
Function
0dB attenuation
45dB attenuation
mute
DS100906-7
FIGURE 7. Start of Audio Input Frame
DS100906-9
FIGURE 8. AC Link Powerdown Timing
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