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參數(shù)資料
| 型號(hào)： | LM4050AI-4.1 |
| 廠商： | National Semiconductor Corporation |
| 元件分類(lèi)： | 串行ADC |
| 英文描述： | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold |
| 中文描述： | 自校準(zhǔn)12位帶符號(hào)串行I /辦公自動(dòng)化/ D轉(zhuǎn)換器MUX和采樣/保持 |
| 文件頁(yè)數(shù)： | 11/41頁(yè) |
| 文件大小： | 1152K |
| 代理商： | LM4050AI-4.1 |
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Note 5:
The human body model is a 100 pF capacitor discharged through a 1.5 k
resistor into each pin.
Note 6:
See AN450 “Surface Mounting Methods and Their Effect on Product Reliability” or the section titled “Surface Mount” found in any post 1986 National
Semiconductor Linear Data Book for other methods of soldering surface mount devices.
Note 7:
Two on-chip diodes are tied to each analog input through a series resistor as shown below. Input voltage magnitude up to 5V above V
+ or 5V below GND
will not damage this device. However, errors in the A/D conversion can occur (if these diodes are forward biased by more than 50 mV) if the input voltage magnitude
of selected or unselected analog input go above V
A
+ or below GND by more than 50 mV. As an example, if V
A
+ is 4.5 V
DC
, full-scale input voltage must be
≤
4.55
V
DC
to ensure accurate conversions.
01135402
Note 8:
To guarantee accuracy, it is required that the V
A
+ and V
D
+ be connected together to the same power supply with separate bypass capacitors at each V
+
pin.
Note 9:
With the test condition for V
REF
(V
REF
+ V
REF
) given as +4.096V, the 12-bit LSB is 1.0 mV and the 8-bit LSB is 16.0 mV.
Note 10:
Typicals are at T
J
= T
A
= 25C and represent most likely parametric norm.
Note 11:
Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 12:
Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error, the straight line passes through negative full-scale and zero (see
Figures 2, 3
).
Note 13:
Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions
between 1 to 0 and 0 to +1 (see
Figure 4
).
Note 14:
Total unadjusted error includes offset, full-scale, linearity and multiplexer errors.
Note 15:
The DC common-mode error is measured in the differential multiplexer mode with the assigned positive and negative input channels shorted together.
Note 16:
Channel leakage current is measured after the channel selection.
Note 17:
Timing specifications are tested at the TTL logic levels, V
IL
= 0.4V for a falling edge and V
IH
= 2.4V for a rising edge. TRI-STATE output voltage is forced
to 1.4V.
Note 18:
The ADC12030 family’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will
result in a maximum repeatability uncertainty of 0.2 LSB.
Note 19:
If SCLK and CCLK are driven from the same clock source, then t
A
is 6, 10, 18 or 34 clock periods minimum and maximum.
Note 20:
The “12-Bit Conversion of Offset” and “12-Bit Conversion of Full-Scale” modes are intended to test the functionality of the device. Therefore, the output
data from these modes are not an indication of the accuracy of a conversion result.
01135410
FIGURE 1. Transfer Characteristic
A
www.national.com
11
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| LM4120AI-4.1 | Self-Calibrating 12-Bit Plus Sign Serial I/O A/D Converters with MUX and Sample/Hold |
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| LM4050AIM3-2.0/NOPB | 功能描述:IC VREF SHUNT PREC 2.048V SOT23 RoHS:是 類(lèi)別:集成電路 (IC) >> PMIC - 電壓基準(zhǔn) 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 基準(zhǔn)類(lèi)型:旁路，精度 輸出電壓:5V 容差:±0.5% 溫度系數(shù):100ppm/°C 輸入電壓:- 通道數(shù):1 電流 - 陰極:80µA 電流 - 靜態(tài):- 電流 - 輸出:15mA 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:TO-236-3，SC-59，SOT-23-3 供應(yīng)商設(shè)備封裝:SOT-23-3 包裝:帶卷 (TR) 其它名稱(chēng):LM4040CIM3-5.0MLTRLM4040CIM3-5.0MLTR-ND |
| LM4050AIM3-2.1 | 制造商:Maxim Integrated Products 功能描述:50PPM/+C PRECISION MICROPOWER SHUNT - Rail/Tube |
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