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參數(shù)資料
| 型號： | LM3881 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Power Sequencer |
| 中文描述： | 電力序 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大?。?/td> | 218K |
| 代理商： | LM3881 |
Application Information
OVERVIEW
The LM3881 Power Sequencer provides a simple solution for
sequencing multiple rails in a controlled manner. A clock sig-
nal is established that facilitates control of the power up and
power down of three open drain FET output flags. These flags
permit connection to shutdown or enable pins of linear regu-
lators and/or switching regulators to control the power sup-
plies’ operation. This allows a complete power system to be
designed without worrying about large in-rush currents or
latch-up conditions that can occur during an uncontrolled
startup. An invert (INV) pin is provided that reverses the logic
of the output flags. This pin should be tied to a logic output
high or low and not allowed to remain open circuit. The fol-
lowing discussion assumes the INV pin is held low such that
the flag output is active high.
A small external timing capacitor is connected to the TADJ
pin that establishes the clock waveform. This capacitor is lin-
early charged/discharged by a fixed current source/sink, de-
noted I
/ I
, of magnitude 12 μA between pre-
defined voltage threshold levels, denoted V
and V
, to
generate the timing waveform as shown in the following dia-
gram.
30048409
FIGURE 1. TADJ Pin Timing Waveform
Thus, the clock cycle duration is directly proportional to the
timing capacitor value. Considering the TADJ voltage thresh-
old levels and the charge/discharge current magnitude, it can
be shown that the timing capacitor-clock period relationship
is typically 120 μs/nF. For example, a 10 nF capacitor sets up
a clock period of 1.2 ms.
The timing sequence of the LM3881 is controlled by the en-
able (EN) pin. Upon power up, all the flags are held low until
the precision enable pin exceeds its threshold. After the EN
pin is asserted, the power up sequence will commence and
the open-drain flags will be sequentially released.
An internal counter will delay the first flag (FLAG1) from rising
until a fixed time period, denoted by T
D1
in the following timing
diagram, elapses. This corresponds to at least nine, maxi-
mum ten, clock cycles depending on where EN is asserted
relative to the clock signal. Upon release of the first flag, an-
other timer will begin to delay the release of the second flag
(FLAG2). This time delay, denoted T
, corresponds to ex-
actly eight clock periods. Similarly, FLAG3 is released after
time delay T
, again eight clock cycles, has expired. Accord-
ingly, a TADJ capacitor of 10 nF generates typical time delays
T
and T
D3
of 9.6 ms and T
D1
of between 10.8 ms and 12.0
ms.
The power down sequence is the same as power up, but in
reverse order. When the EN pin is de-asserted, a timer will
begin that delays the third flag (FLAG3) from pulling low. The
second and first flag will then follow in a sequential manner
after their appropriate time delays. These time delays, denot-
ed T
D4
, T
D5
, T
D6
, are equal to T
D1
, T
D2
, T
D3
, respectively.
For robustness, the pull down FET associated with each flag
is designed such that it can sustain a short circuit to VCC.
7
www.national.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM3881EVAL | 功能描述:電源管理IC開發(fā)工具 LM3881 EVAL BOARD RoHS:否 制造商:Maxim Integrated 產(chǎn)品:Evaluation Kits 類型:Battery Management 工具用于評估:MAX17710GB 輸入電壓: 輸出電壓:1.8 V |
| LM3881EVAL | 制造商:Texas Instruments 功能描述:EVAL BOARD, LM3881, POWER SEQUENCER |
| LM3881MM | 制造商:Texas Instruments 功能描述:Power Sequencer 8-Pin MSOP T/R 制造商:Texas Instruments 功能描述:IC, POWER SEQUENCER, 2.7 TO 5.5V |
| LM3881MM/NOPB | 功能描述:監(jiān)控電路 POWER SEQUENCER RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關(guān):No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| LM3881MME | 制造商:Texas Instruments 功能描述:Power Sequencer T/R |
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