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參數資料
| 型號： | LM3880MF-1AC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 模擬信號調理 |
| 英文描述： | Power Sequencer |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO6 |
| 封裝： | SOT-23, 6 PIN |
| 文件頁數： | 7/12頁 |
| 文件大?。?/td> | 216K |
| 代理商： | LM3880MF-1AC |
Timing Diagrams (Sequence 1)
All standard options use this sequence for output flags rise and fall order.
20192613
Power Up Sequence
20192614
Power Down Sequence
Application Information
OVERVIEW
The LM3880 Power Sequencer provides an easy solution for
sequencing multiple rails in a controlled manner. Six inde-
pendent timers are integrated to control the timing sequence
(power up and power down) of three open drain output flags.
These flags permit connection to either a shutdown / enable
pin of linear regulators and switchers to control the power
supplies’ operation. This allows a complete power system to
be designed without worrying about large in-rush currents or
latch-up conditions that can occur.
The timing sequence of the LM3880 is controlled entirely by
the enable (EN) pin. Upon power up, all the flags are held low
until this precision enable is pulled high. After the EN pin is
asserted, the power up sequence will commence. An internal
counter will delay the first flag (FLAG1) from rising until a fixed
time period has expired. Upon the release of the first flag an-
other timer will begin to delay the release of the second flag
(FLAG2). This process repeats until all three flags have se-
quentially been released. The three timers that control the
delays are all independent of each other and can be individ-
ually programmed if needed. (See custom sequencer sec-
tion).
The power down sequence is the same as power-up, but in
reverse. When EN pin is de-asserted a timer will begin that
delays the third flag (FLAG3) from pulling low. The second
and first flag will then follow in a sequential manner after their
appropriate delays. The three timers that are used to control
the power down scheme can also be individually programmed
and are completely independent of the power up timers.
Additional sequence patterns are also available in addition to
customizable timers. For more information see the custom
sequencer section.
PART OPERATION
The timing sequence of the LM3880 is controlled by the as-
sertion of the enable signal. The enable pin is designed with
an internal comparator, referenced to a bandgap voltage
(1.25V), to provide a precision threshold. This allows a de-
layed timing to be externally set using a capacitor or to start
the sequencing based on a certain event, such as a line volt-
age reaching 90% of nominal. For an additional delayed
sequence from the rail powering VCC, simply attach a ca-
pacitor to the EN pin as shown below.
7
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LM3880MF-1AC/NOPB | 功能描述:監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數: 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| LM3880MF-1AD | 制造商:Texas Instruments 功能描述:Volt Supervisor Sequencer 6-Pin SOT-23 T/R 制造商:Texas Instruments 功能描述:Power Sequencer,3 Outputs,120ms,SOT23-6 |
| LM3880MF-1AD/NOPB | 功能描述:監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數: 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
| LM3880MF-1AE | 制造商:Texas Instruments 功能描述:Volt Supervisor Sequencer 6-Pin SOT-23 T/R |
| LM3880MF-1AE/NOPB | 功能描述:監(jiān)控電路 RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數: 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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