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參數(shù)資料
| 型號(hào)： | LM2665M6 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Switched Capacitor Voltage Converter |
| 中文描述： | SWITCHED CAPACITOR CONVERTER, 160 kHz SWITCHING FREQ-MAX, PDSO6 |
| 封裝： | SOT-23, 6 PIN |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 210K |
| 代理商： | LM2665M6 |
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V+ to GND, or GND to OUT)
SD
5.8V
(GND 0.3V) to (V+ +
0.3V)
50 mA
1 sec.
V+ and OUT Continuous Output Current
Output Short-Circuit Duration to GND (Note 2)
Continuous Power
Dissipation (T
A
= 25C)(Note 3)
T
JMax
(Note 3)
θ
JA
(Note 3)
Operating Junction
Temperature Range
Storage Temperature Range
Lead Temp. (Soldering, 10 seconds)
ESD Rating
600 mW
150C
210C/W
40 to 85C
65C to +150C
300C
2kV
Electrical Characteristics
Limits in standard typeface are for T
J
= 25C, and limits in
boldface
type apply over the full operating temperature range. Un-
less otherwise specified: V+ = 5V, C
1
= C
2
= 3.3 μF. (Note 4)
Symbol
Parameter
Condition
V+
Supply Voltage
I
Q
Supply Current
No Load
I
SD
Shutdown Supply Current
V
SD
Shutdown Pin Input Voltage
Shutdown Mode
Min
2.5
Typ
Max
5.5
1250
Units
V
μA
μA
650
1
2.0
(Note 5)
V
Normal Operation
0.8
(Note 6)
I
L
R
SW
Output Current
Sum of the R
ds(on)
of the four
internal MOSFET switches
Output Resistance (Note 7)
Oscillator Frequency
Switching Frequency
Power Efficiency
40
mA
I
L
= 40 mA
3.5
8
R
OUT
f
OSC
f
SW
P
EFF
I
L
= 40 mA
(Note 8)
(Note 8)
R
L
(1.0k) between GND and
OUT
I
L
= 40 mA to GND
No Load
12
160
80
25
80
40
kHz
kHz
86
93
%
90
V
OEFF
Note 1:
Absolute maximum ratings indicate limits beyond which damage to the device may occur. Electrical specifications do not apply when operating the device
beyond its rated operating conditions.
Note 2:
OUT may be shorted to GND for one second without damage. However, shorting OUT to V+ may damage the device and should be avoided. Also, for tem-
peratures above 85C, OUT must not be shorted to GND or V+, or device may be damaged.
Note 3:
The maximum allowable power dissipation is calculated by using P
DMax
= (T
JMax
T
A
)/
θ
JA
, where T
JMax
is the maximum junction temperature, T
A
is the
ambient temperature, and
θ
JA
is the junction-to-ambient thermal resistance of the specified package.
Note 4:
In the test circuit, capacitors C
1
and C
2
are 3.3 μF, 0.3
maximum ESR capacitors. Capacitors with higher ESR will increase output resistance, reduce output
voltage and efficiency.
Note 5:
The minimum input high for the shutdown pin equals 40% of V+.
Note 6:
The maximum input low of the shutdown pin equals 20% of V+.
Note 7:
Specified output resistance includes internal switch resistance and capacitor ESR. See the details in the application information for positive voltage doubler.
Note 8:
The output switches operate at one half of the oscillator frequency, f
OSC
= 2f
SW
.
Voltage Conversion Efficiency
99
99.96
%
L
www.national.com
2
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