Application Information
(Continued)
the upper FET sees the V-I crossover losses (at turn-ON and
at turn-OFF). So to maximize efficiency, high switching
speed is certainly needed in this position. This FET position
has typically very low conduction losses, especially in a
power supply for mobile applications since the duty cycle is
very low. So the Rds is not of much direct concern here. A
possible choice of FET for the upper position on the Evalu-
ation board is the Si4800DY from Vishay (www.vishay.com).
The threshold voltage (MIN value) of a FET in this position
can be 0.8V but 1.0V is preferable. Note however that if the
upper FET is chosen so that it switches too fast, it can induce
a shoot-through (called a CdV/dt turn-on of the lower FET)
whenever the upper FET turns on hard. Therefore, Q
G
of the
upper FET should not be much less than 8nC.
b) The lower FET sees no V-I crossover loss in principle
(under most situations). Also, since it can conduct for the
complete OFF-time, its Rds becomes important, especially
at low duty cycles. This FET is therefore chosen basically for
its low Rds, not necessarily speed. A high C
for this FET
position also helps, by reducing the possibility of CdV/dt
turn-on of this FET, by snubbing the rising edge of voltage
applied on the lower FET when the upper FET turns ON.
Note that too high a C
value will degrade efficiency. An
acceptable compromise figure for C
OSS
of the lower FET is
350-800pF. A possible choice of FET for this position is the
Si4420DY from Vishay. The C
OSS
of this FET is about 700pF
at 24V. The threshold voltage for the lower FET position
must also be 1V or slightly higher. Too high a threshold will
prevent the FET from turning ON fully, and too low a value
will increase the likelihood of a CdV/dt turn-on.Also note that
one of the factors which can provoke a spurious turn-on is
layout. In particular, the source lead/trace of a given FET
must be kept short and the copper area around it large to
reduce inductive spikes during transitions. Gate trace
lengths must also be kept short.
Note that the threshold voltage of a FET should have both
MIN and MAX limits as per its datasheet. Since it is important
that the FET turn on fully, ensure that the threshold voltage is
guaranteed to be below 3V. Contact the FET vendor if nec-
essary. If the threshold voltage is too high, foldback might
result upon hitiing current limit. This will result in failure of the
output to recover after an overload condition.
EFFICIENCY ESTIMATE
A sample calculation follows based on the low cost FETs
used on the Evaluation Board. The device is the Si4828DY
from Vishay.
The extension ’_u’ stands for the upper FET (half
Si4828DY), and ’_l’ for the lower FET (half Si4828DY). The
general equation is first stated and then the numerical result
is quoted (in bold). The case is for V
IN
=20V, Vo=5V, Io=3A.
The frequency is set to 300kHz. Note that efficiency esti-
mates are usually based on typical values. Therefore, in the
calculations below the typical value of the gate charge Q
G
is
used. For the Si4828DY the typical values as declared in its
datasheet (available at the time of writing this section) are
Q
G
(upper) = 8nC, Q
G
(lower) = 23nC, Rds(upper) = 24m
,
Rds(lower) = 14.5m
FET Conduction losses
Pcond_u = 54mW
Pcond_l = 98mW
FET Switching Losses
The transition times must first be determined. A simplified
equation available in related literature is:
This equation is applied to our case by setting the pulse
amplitude Vp to 5V. Suppose the output impedances of the
IC are (in ohms):
Rpon_u = 7
Rpoff_u = 2
Rpon_l = 7
Rpoff_l = 1
Therefore transition times are
ton_u = 51.5ns
toff_u = 15ns
ton_l = 148ns
toff_l = 21ns
The switching loss for any V-I crossover when driving an
inductive load is in general
Pcross = 1/2 x V x I x tcross x freq
L
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