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參數(shù)資料
| 型號： | LM1886N |
| 英文描述： | Color Encoder Circuit |
| 中文描述： | 顏色編碼器電路 |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 172K |
| 代理商： | LM1886N |
Application Notes
(Continued)
half line). Remember this pulse is a positive pulse at the
integrator but negative in Figure 2. This graph shows how
long it takes the integrator to charge its internal capacitor
above V
1
.
WITH R
set
too large the charging current of the integrator
will be too small to charge the capacitor above V
1
, thus
there will be no vertical synch output pulse. As mentioned
above, R
set
also sets the frequency of the internal oscillator.
If the oscillator runs too fast its eight cycles will be shorter
than the vertical sync portion of the composite sync. Under
this condition another vertical sync pulse can be generated
on one of the later serration pulses after the divide by 8
circuit resets the R/S flip-flop. The first graph also shows
the minimum R
set
necessary to prevent a double vertical
pulse, assuming that the serration pulses last for only three
full horizontal line periods (six serration pulses for NTSC).
The actual pulse width of the vertical sync pulse is shown in
the ‘‘Vertical Pulse Width vs R
set
’’ graph. Using NTSC as an
example, lets see how these two graphs relate to each oth-
er. The Horizontal line is 64
m
s long, or 32
m
s for a horizon-
tal half line. Now round this off to 30
m
s. In the ‘‘R
set
Value
Selection vs Vertical Serration Pulse Separation’’ graph the
minimum resistor value for 30
m
s serration pulse separation
is about 550 k
X
. Going to the ‘‘Vertical Pulse Width vs R
set
’’
graph one can see that 550 k
X
gives a vertical pulse width
of about 180
m
s, the total time for the vertical sync period of
NTSC (3 horizontal lines). A 550 k
X
will set the internal
oscillator to a frequency such that eight cycles gives a time
of 180
m
s, just long enough to prevent a double vertical
sync pulse at the vertical sync output of the LM1881.
The LM1881 also generates a default vertical sync pulse
when the vertical sync period is unusually long and has no
serration pulses. With a very long vertical sync time the inte-
grator has time to charge its internal capacitor above the
voltage level V
2
. Since there is no falling edge at the end of
a serration pulse to clock the ‘‘D’’ flip-flop, the only high
signal going to the OR gate is from the default comparator
when output of the integrator reaches V
2
. At this time the
R/S flip-flop is toggled by the default comparator, starting
the vertical sync pulse at pin 3 of the LM1881. If the default
vertical sync period ends before the end of the input vertical
sync period, then the falling edge of the vertical sync (posi-
tive pulse at the ‘‘D’’ flip-flop) will clock the high output from
the comparator with V
1
as a reference input. This will retrig-
ger the oscillator, generating a second vertical sync output
pulse. The ‘‘Vertical Default Sync Delay Time vs R
set
’’
graph shows the relationship between the R
set
value and
the delay time from the start of the vertical sync period be-
fore the default vertical sync pulse is generated. Using the
NTSC example again the smallest resistor for R
set
is 500
k
X
. The vertical default time delay is about 50
m
s, much
longer than the 30
m
s serration pulse spacing.
A common question is how can one calculate the required
R
set
with a video timing standard that has no serration puls-
es during the vertical blanking. If the default vertical sync is
to be used this is a very easy task. Use the ‘‘Vertical Default
Sync Delay Time vs R
set
’’ graph to select the necessary
R
set
to give the desired delay time for the vertical sync out-
put signal. If a second pulse is undesirable, then check the
‘‘Vertical Pulse Width vs R
set
’’ graph to make sure the verti-
cal output pulse will extend beyond the end of the input
vertical sync period. In most systems the end of the vertical
sync period may be very accurate. In this case the preferred
design may be to start the vertical sync pulse at the end of
the vertical sync period, similar to starting the vertical sync
pulse after the first serration pulse. A VGA standard is to be
used as an example to show how this is done. In this stan-
dard a horizontal line is 32
m
s long. The vertical sync period
is two horizontal lines long, or 64
m
s. The vertical default
sync delay time
must be longer
than the vertical sync peri-
od of 64
m
s. In this case R
set
must be larger than 680 k
X
.
R
set
must still be small enough for the output of the integra-
tor to reach V
1
before the end of the vertical period of the
input pulse. The first graph can be used to confirm that R
set
is small enough for the integrator. Instead of using the verti-
cal serration pulse separation, use the actual pulse width of
the vertical sync period, or 64
m
s in this example. This graph
is linear, meaning that a value as large as 2.7 M
X
can be
used for R
set
(twice the value as the maximum at 30
m
s).
Due to leakage currents it is advisable to keep the value of
R
set
under 2.0 M
X
. In this example a value of 1.0 M
X
is
selected, well above the minimum of 680 k
X
. With this value
for R
set
the pulse width of the vertical sync output pulse of
the LM1881 is about 340
m
s.
ODD/EVEN FIELD PULSE
An unusual feature of LM1881 is an output level from Pin 7
that identifies the video field present at the input to the
LM1881. This can be useful in frame memory storage appli-
cations or in extracting test signals that occur only in alter-
nate fields. For a composite video signal that is interlaced,
one of the two fields that make up each video frame or
picture must have a half horizontal scan line period at the
end of the vertical scanDi.e., at the bottom of the picture.
This is called the ‘‘odd field’’ or ‘‘field 1’’. The ‘‘even field’’
or ‘‘field 2’’ has a complete horizontal scan line at the end of
the field. An odd field starts on the leading edge of the first
equalizing pulse, whereas the even field starts on the lead-
ing edge of the second equalizing pulse of the vertical re-
trace interval. Figure 2(a) shows the end of the even field
and the start of the odd field.
To detect the odd/even fields the LM1881 again integrates
the composite sync waveform (Figure 3). A capacitor is
charged during the period between sync pulses and dis-
charged when the sync pulse is present. The period be-
tween normal horizontal sync pulses is enough to allow the
capacitor voltage to reach a threshold level of a comparator
that clears a flipflop which is also being clocked by the sync
waveform. When the vertical interval is reached, the shorter
integration time between equalizing pulses prevents this
6
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