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參數(shù)資料
| 型號： | LM1881MX |
| 英文描述： | TV/Video Sync Circuit |
| 中文描述： | 電視/視頻同步電路 |
| 文件頁數(shù)： | 4/10頁 |
| 文件大小： | 172K |
| 代理商： | LM1881MX |
Application Notes
The LM1881 is designed to strip the synchronization signals
from composite video sources that are in, or similar to, the
N.T.S.C. format. Input signals with positive polarity video (in-
creasing signal voltage signifies increasing scene bright-
ness) from 0.5V (p-p) to 2V (p-p) can be accommodated.
The LM1881 operates from a single supply voltage between
5V DC and 12V DC. The only required external components
beside power supply and set current decoupling are the in-
put coupling capacitor and a single resistor that sets internal
current levels, allowing the LM1881 to be adjusted for
source signals with line scan frequencies differing from
15.734 kHz. Four major sync signals are available from the
I/C: composite sync including both horizontal and vertical
scan timing information; a vertical sync pulse; a burst gate
or back porch clamp pulse; and an odd/even output. The
odd/even output level identifies which video field of an inter-
laced video source is present at the input. The outputs from
the LM1881 can be used to gen-lock video camera/VTR
signals with graphics sources, provide identification of video
fields for memory storage, recover suppressed or contami-
nated sync signals, and provide timing references for the
extraction of coded or uncoded data on specific video scan
lines.
To better understand the LM1881 timing information and
the type of signals that are used, refer to Figure 2(a–e)
which shows a portion of the composite video signal from
the end of one field through the beginning of the next field.
COMPOSITE SYNC OUTPUT
The composite sync output, Figure 2(b), is simply a repro-
duction of the signal waveform below the composite video
black level, with the video completely removed. This is ob-
tained by clamping the video signal sync tips to 1.5V DC at
Pin 2 and using a comparator threshold set just above this
voltage to strip the sync signal, which is then buffered out to
Pin 1. The threshold separation from the clamped sync tip is
nominally 70 mV which means that for the minimum input
level of 0.5V (p-p), the clipping level is close to the halfway
point on the sync pulse amplitude (shown by the dashed
line on Figure 2(a) ). This threshold separation is indepen-
dent of the signal amplitude, therefore, for a 2V (p-p) input
the clipping level occurs at 11% of the sync pulse ampli-
tude. The charging current for the input coupling capacitor is
0.8 mA, whereas the discharge current is only 11
m
A, typi-
cally. This allows relatively small capacitor values to be
usedD0.1
m
F is generally recommended.
Normally the signal source for the LM1881 is assumed to be
clean and relatively noise-free, but some sources may have
excessive video peaking, causing high frequency video and
chroma components to extend below the black level refer-
ence. Some video discs keep the chroma burst pulse pres-
ent throughout the vertical blanking period so that the burst
actually appears on the sync tips for three line periods in-
stead of at black level. A clean composite sync signal can
be generated from these sources by filtering the input sig-
nal. When the source impedance is low, typically 75
X
, a
620
X
resistor in series with the source and a 510 pF capaci-
tor to ground will form a low pass filter with a corner fre-
quency of 500 kHz. This bandwidth is more than sufficient to
pass the sync pulse portion of the waveform; however, any
subcarrier content in the signal will be attenuated by almost
18 dB, effectively taking it below the comparator threshold.
Filtering will also help if the source is contaminated with
thermal noise. The output waveforms will become delayed
from between 40 ns to as much as 200 ns due to this filter.
This much delay will not usually be significant but it does
contribute to the sync delay produced by any additional sig-
nal processing. Since the original video may also undergo
processing, the need for time delay correction will depend
on the total system, not just the sync stripper.
VERTICAL SYNC OUTPUT
A vertical sync output is derived by internally integrating the
composite sync waveform (Figure 3). To understand the
generation of the vertical sync pulse, refer to the lower left
hand sectionFigure 3. Note that there are two comparators
in the section. One comparator has an internally generated
voltage reference called V
1
going to one of its inputs. The
other comparator has an internally generated voltage refer-
ance called V
2
going to one of its inputs. Both comparators
have a common input at their noninverting input coming
from the internal integrator. The internal integrator is used
for integrating the composite sync signal. This signal comes
from the input side of the composite sync buffer and are
positive
going sync pulses. The capacitor to the integrator
is internal to the LM1881. The capacitor charge current is
set by the value of the external resistor R
set
. The output of
the integrator is going to be at a low voltage during the
normal horizontal lines because the integrator has a very
short time to charge the capacitor, which is during the hori-
zontal sync period. The equalization pulses will keep the
output voltage of the integrator at about the same level,
below the V
1
. During the vertical sync period the narrow
going positive pulses shown in Figure 2 is called the serra-
tion pulse. The wide negative portion of the vertical sync
period is called the vertical sync pulse. At the start of the
vertical sync period, before the first Serration pulse occurs,
the integrator now charges the capacitor to a much higher
voltage. At the first serration pulse the integrator output
should be between V
1
and V
2
. This would give a high level
at the output of the comparator with V
1
as one of its inputs.
This high is clocked into the ‘‘D’’ flip-flop by the falling edge
of the serration pulse (remember the sync signal is inverted
in this section of the LM1881). The ‘‘Q’’ output of the ‘‘D’’
flip-flop goes through the OR gate, and sets the R/S flip-
flop. The output of the R/S flip-flop enables the internal
oscillator and also clocks the ODD/EVEN ‘‘D’’ flip-flop. The
ODD/EVEN field pulse operation is covered in the next sec-
tion. The output of the oscillator goes to a divide by 8 circuit,
thus resetting the R/S flip-flop after 8 cycles of the oscilla-
tor. The frequency of the oscillator is established by the
internal capacitor going to the oscillator and the external
R
set
. The ‘‘Q’’ output of the R/S flip-flop goes to pin 3 and is
the actual vertical sync output of the LM1881. By clocking
the ‘‘D’’ flip-flop at the start of the first serration pulse
means that the vertical sync output pulse starts at this point
in time and lasts for eight cycles of the internal oscillator as
shown in Figure 2.
How R
set
affects the integrator and the internal oscillator is
shown under the Typical Performance Characteristics. The
first graph is ‘‘R
set
Value Selection vs Vertical Serration
Pulse Separation’’. For this graph to be valid, the vertical
sync pulse should last for at least 85% of the horizontal half
line (47% of a full horizontal line). A vertical sync pulse from
any standard should meet this requirement; both NTSC and
PAL do meet this requirement (the serration pulse is the
remainder of the period, 10% to 15% of the horizontal
4
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM1881M-X | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:LM1881 Video Sync Separator |
| LM1881MX/NOPB | 功能描述:視頻 IC VIDEO SYNC SEPARATOR RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
| LM1881M-X/NOPB | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| LM1881MX-X/NOPB | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| LM1881N | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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