參數(shù)資料
型號(hào): LM12L458CIV
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 模擬信號(hào)調(diào)理
英文描述: 12-Bit Sign Data Acquisition System with Self-Calibration
中文描述: SPECIALTY ANALOG CIRCUIT, PQCC44
封裝: PLASTIC, LCC-44
文件頁數(shù): 4/36頁
文件大?。?/td> 695K
代理商: LM12L458CIV
Converter Characteristics
(Continued)
The following specifications apply for V
+ = V
D
+ = 3.3V, V
REF+
= 2.5V, V
= 0V, 12-bit + sign conversion mode, f
=
6.0 MHz, R
= 25
, source impedance for V
and V
25
, fully-differential input with fixed 1.25V common-mode volt-
age, and minimum acquisition time unless otherwise specified.
Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other
limits T
A
= T
J
= 25C. (Notes 6, 7, 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
Limits
(Note 11)
GND
V
A
+
V
A+
V
A
+
GND
V
A
+
±
1.75
±
2
Unit
(Limit)
V (min)
V (max)
V (min)
V (max)
V (min)
V (max)
LSB (max)
LSB (max)
LSB
pF
pF
V
IN
Inverting Input Range
V
IN+
V
IN
Differential Input Voltage Range
Common Mode Input Voltage Range
PSS
Power Supply
Sensitivity
(Note 15)
V
REF+
/V
REF
Input Capacitance
Selected Multiplexer Channel Input
Capacitance
Zero Error
Full-Scale Error
Linearity Error
V
A
+ = V
D
+ = 3.3V
±
10%
V
REF+
= 2.5V, V
REF
= GND
±
0.2
±
0.4
±
0.2
85
C
REF
C
IN
75
Converter AC Characteristics
The following specifications apply for V
A
+ = V
D
+ = 3.3V, V
REF+
= 2.5V, V
= 0V, 12-bit + sign conversion mode, f
= 6.0
MHz, R
= 25
, source impedance for V
and V
, fully-differential input with fixed 1.25V common-mode voltage,
and minimum acquisition time unless otherwise specified.
Boldface limits apply for T
A
= T
J
= T
MIN
to T
MAX
; all other limits
T
A
= T
J
= 25C. (Notes 6, 7, 8, 9)
Symbol
Parameter
Conditions
Typical
(Note 10)
50
Limits
(Note 11)
Unit
(Limit)
%
% (min)
% (max)
(max)
Clock Duty Cycle
40
60
t
C
Conversion Time
13-Bit Resolution,
Sequencer State S5 (Figure 15)
9-Bit Resolution,
Sequencer State S5 (Figure 15)
Sequencer State S7 (Figure 15)
Built-in minimum for 13-Bits
Built-in minimum for 9-Bits and
“Watchdog” mode
Sequencer State S2 (Figure 15)
Sequencer State S2 (Figure 15)
44 (t
CLK
)
44 (t
CLK
) + 50 ns
21 (t
CLK
)
21 (t
CLK
) + 50 ns
(max)
t
A
Acquisition Time
9 (t
CLK
)
9 (t
CLK
) + 50 ns
(max)
2 (t
CLK
)
2 (t
CLK
) + 50 ns
(max)
t
Z
t
CAL
Auto-Zero Time
Full Calibration Time
Throughput Rate
(Note 18)
“Watchdog” Mode
Comparison Time
Power-Up Time
Wake-Up Time
76 (t
CLK
)
4944 (t
CLK
)
76 (t
CLK
) + 50 ns
4944 (t
CLK
) + 50 ns
(max)
(max)
kHz
(min)
(max)
107
106
t
WD
Sequencer States S6, S4,
and S5 (Figure 15)
11 (t
CLK
)
11 (t
CLK
) + 50 ns
t
PU
t
WU
10
10
ms
ms
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