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參數(shù)資料
| 型號： | LM1276AAA |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 150 MHz I2C Compatible RGB Preamplifier with Internal 512 Character OSD ROM, 512 Character RAM and 4 DACs |
| 中文描述： | 150 MHz的I2C兼容的RGB前置放大器512個字符OSD光盤，512個字符RAM和4 DAC的內(nèi)置 |
| 文件頁數(shù)： | 32/50頁 |
| 文件大?。?/td> | 2597K |
| 代理商： | LM1276AAA |
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Building Display Pages
(Continued)
The Page RAM address is not automatically incremented in this mode. This mode is very useful for modifying character codes
and attributes in the first 256 locations of the Page RAM. The attribute byte is shown in
Table 19
, and the sequence of transmitted
bytes is shown in
Table 20
. Either another LSB address & attribute & character code or a STOP must follow after each character
code.
TABLE 19. Half Random Address Mode
ATTRIBUTE Byte
CC[8]
X
1
0
ATT[3:0]
TABLE 20. Sequence of Transmitted Bytes
FULL RANDOM ADDRESS MODE
The Full RandomAddress mode is very similar to the Half RandomAddress mode. However, the advantage is that the Page RAM
addresses can now be entirely random. There is no longer a restriction to only one half of the Page RAM. The Page RAM address
is not automatically incremented in this mode. This is very useful for modifying character codes and attributes anywhere in the
Page RAM without starting a new transmission sequence. The Full Random Address mode is the most flexible mode of
transmission. The attribute byte is shown in
Table 21
, and the sequence of transmitted bytes is shown in
Table 22
. Either another
LSB address & MSB address & attribute & character code or a STOP must follow after each character code.
TABLE 21. Full Random Address Mode
ATTRIBUTE Byte
CC[8]
X
1
1
ATT[3:0]
TABLE 22. Sequence of Transmitted Bytes
Control Register Definitions
OSD INTERFACE REGISTERS
Frame Control Register 1:
FRMCTRL1 (0x8400)
Fade
I/O
Trans
FEN
TD
Autosize
done
ASZDN
Autosize
ASZEN
Clear
CDPR
Win2
D2E
Win1
D1E
OSD
OSE
Bit 0
On-Screen Display Enable. The On-Screen Display will be disabled when this bit is a zero. When this bit is a one
the On-Screen Display will be enabled. This controls both Window 1 and Window 2.
Display Window 1 Enable. When this bit and Bit 0 of this register are both ones, Display Window 1 is enabled. If
either bit is a zero, then Display Window 1 will be disabled.
Display Window 2 Enable. When this bit and Bit 0 of this register are both ones, Display Window 2 is enabled. If
either bit is a zero, then Display Window 2 will be disabled.
Clear Display Page RAM. Writing a one to this bit will result in setting all of the Display Page RAM values to zero.
This bit is automatically cleared after the operation is complete. This bit is initially asserted by default at power up,
and will clear itself back to zero shortly after. Thus, the default value is one only momentarily, and then will remain
zero until manually asserted again or until the power is cycled.
Transparent Disable. When this bit is a zero, a palette color of black (i.e., color palette look-up table value of 0x00)
in the first 8 palette look-up table address locations (i.e., ATT0–ATT7) will be interpreted as transparent. When this
bit is a one, the color will be interpreted as black.
Bit 1
Bit 2
Bit 3
Bit 4
L
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