參數(shù)資料
型號(hào): LM1276
廠商: National Semiconductor Corporation
英文描述: 150 MHz I2C Compatible RGB Preamplifier with Internal 512 Character OSD ROM, 512 Character RAM and 4 DACs
中文描述: 150 MHz的I2C兼容的RGB前置放大器512個(gè)字符OSD光盤,512個(gè)字符RAM和4 DAC的內(nèi)置
文件頁數(shù): 28/50頁
文件大小: 2597K
代理商: LM1276
LM1276 Address Map
(Continued)
TABLE 10. End-Of-Screen Code
ATTRIBUTE CODE
ATT[3:0]
END-OF-SCREEN CODE
0
0
0
0
0
0
0
0
0
Bits 8–0 are all zeros. Bits 12–9 will have the previously entered AC but this is not used and so these bits are “don’t cares”.
OSD CONTROL REGISTERS
These registers, shown in
Table 11
, control the size, position, enhanced features and ROM bank selection of up to two
independent OSD windows.
These registers are compatible to the LM1246 OSD control Registers.
Any bits marked as “X”
are reserved and should be written to with zeros and should be ignored when the register is read. Additional register detail is
provided in the
Control Register Definitions Section,
later in this document.
TABLE 11. OSD Control Register Detail
Register
FRMCTRL1
FRMCTRL2
CHARFONTACC
VBLANKDUR
CHARHTCTRL
BBHLCTRLB0
BBHLCTRLB1
BBLLCTRLB0
BBLLCTRLB1
CHSDWCTRLB0
CHSDWCTRLB1
ROMSIGCTRL
ROMSIGDATAB0
ROMSIGDATAB1
HSTRT1
VSTRT1
W1STRTADRL
W1STRTADRH
COLWIDTH1B0
COLWIDTH1B1
COLWIDTH1B2
COLWIDTH1B3
HSTRT2
VSTRT2
W2STRTADRL
W2STRTADRH
COLWIDTH2B0
COLWIDTH2B1
COLWIDTH2B2
COLWIDTH2B3
Any registers in the range of 0x8420–0x8426 are for National Semiconductor internal use only and should not be written to under
application conditions.
FADE_INTVL
0x8429
0x35
V_INTVL[3:0]
Address
0x8400
0x8401
0x8402
0x8403
0x8404
0x8405
0x8406
0x8407
0x8408
0x8409
0x840A
0x840D
0x840E
0x840F
0x8410
0x8411
0x8412
0x8413
0x8414
0x8415
0x8416
0x8417
0x8418
0x8419
0x841A
0x841B
0x841C
0x841D
0x841E
0x841F
Default
0x98
0x80
0x00
0x10
0x51
0xFF
0x01
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x62
0x32
0x00
0x00
0x00
0x00
0x00
0x00
0x56
0x5B
0x00
0x01
0x00
0x00
0x00
0x00
D7
D6
D5
FEN
D4
TD
D3
D2
D2E
D1
D1E
D0
OSE
ASZDN
PIXELS_PER_LINE[2:0]
SRST
RSV
X
ASZEN
CDPR
BLINK_PERIOD[4:0]
VSYPOL
HSYPOL
VBLANK_DURATION[6:0]
CHAR_HEIGHT[7:0]
R[2:0]
X
X
R[2:0]
X
X
R[2:0]
X
X
X
X
CRC[7:0]
CRC[15:8]
HPOS1[7:0]
VPOS1[7:0]
ADDR1[7:0]
X
X
COL1[7:0]
COL1[15:8]
COL1[23:16]
COL1[31:24]
HPOS2[7:0]
VPOS2[7:0]
ADDR2[7:0]
X
X
COL2[7:0]
COL2[15:8]
COL2[23:16]
COL2[31:24]
RSV
LIMIT
ATTR
FONT4
G[1:0]
B[2:0]
X
B[2:0]
X
B[2:0]
X
X
X
X
X
X
G[2]
G[1:0]
X
X
X
X
G[2]
G[1:0]
X
X
X
X
X
X
X
X
G[2]
CRS
X
X
X
X
X
ADDR1[8]
X
X
X
X
X
ADDR2[8]
H_INVTVL[3:0]
PREAMPLIFIER CONTROL
These registers, shown in
Table 12
, control the gains, DAC outputs, PLL, horizontal and vertical blanking, OSD contrast and DC
offset of the video outputs.
Registers 0x8430–0x8437 are compatible to the LM1246 Registers.
Any bits marked as “X” are
reserved and should be written to with zeros and should be ignored when the register is read.Additional register detail is provided
in the
Control Register Definitions Section
, later in this document.
L
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