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參數(shù)資料
| 型號： | LM1270NA |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Hi-Brite 200 MHz I2C Compatible RGB Image Enhancer with Video Auto Sizing |
| 中文描述： | 高亮度場致200兆赫與I2C兼容的RGB視頻自動上漿圖像增強(qiáng) |
| 文件頁數(shù)： | 11/27頁 |
| 文件大?。?/td> | 1302K |
| 代理商： | LM1270NA |
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Video Detection
(Continued)
sate for clocking delays in the timing counters in the
LM1270. This value is empirically derived from testing the
video system.
VIDEO INPUT DETECTION
The outputs of the three video detector channels are OR’d
together to provide a single composite signal of the three
channels when used for timing parameter measurement.
The video detect logic must find the extreme points of the
displayed image during each frame with respect to the hori-
zontal and vertical flyback pulses as measured using the
internal PLL. For best performance in autosizing mode, it is
recommended that the application use the maximum number
of pixels per line when measurements are made. Remem-
ber, the VCO frequency is limited to 160 MHz when the
prescaler is set to 7.
The durations to be measured are shown generically in the
figures below, and apply to both horizontal and vertical tim-
ings. For the horizontal timings the measurements will de-
pend on the mode selected in the EMPHASIS register. Ver-
tical and HFLYBACK timing measurements will be the same
in both modes.
1.
Flyback or sync period: the duration of either the sync
input or the horizontal flyback, in either horizontal lines
(vertical) or pixels (horizontal).
Back porch period: the duration between the trailing
edge of the sync or flyback pulse and the leading edge
of the first detected video, in either lines (vertical) or
pixels (horizontal).
Video period: the duration between the leading edge of
the first detected video and the trailing edge of the last
detected video, in either lines (vertical) or pixels (hori-
zontal).
Front porch: the duration between the trailing edge of
the last detected video and the leading edge of the sync
or flyback pulse, in either lines (vertical) or pixels (hori-
zontal).
Note:
In the horizontal timing measurement description, reference to sync
means either HSYNC or H_FEEDBACK, selected by WCHE bit in the
EMPHASIS register.
As the video may start and finish at different positions on the
screen, depending upon the image, the measured horizontal
porches and video time may vary from line to line. To over-
come this, the periods should be measured over at least one
entire field. The hardware records the shortest back porch
and front porch periods used over the measured period.
2.
3.
4.
WINDOW COORDINATE DATA
The microcontroller must program the highlight window co-
ordinates in the LM1270 by writing to the appropriate regis-
ters. The coordinate values must be sent from the PC. For
maximum flexibility, the LM1270 is designed to allow opera-
tion such that the coordinate data may be sent by:
1.
DDC2A/B (e.g., I
2
C compatible) transmission
2.
Information carried as video data during the vertical
blanking time
3.
Any other PC-monitor interface (e.g., USB)
COORDINATE DATA TRANSMISSION BY VIDEO
OPERATION
When sending coordinate data by video please refer to the
information for register 27 in the register descriptions. Any
video line may be selected for data, clock, or window. It is
important to make sure each video line has a different se-
lection otherwise the video transmission of data will not
function. It is possible to program two video channels to
carry the same information and create this incorrect opera-
tion.
If the LIMIT bit of the TEST1 register is set to a “1” (default
value), then one line of data may be transmitted after the
vertical sync on one of the video channels. This data must be
sent during the vertical blanking time that is set by the
vertical blanking register. Data must be transmitted only
during the vertical blanking time otherwise it will be ignored
by the logic. If the LIMIT bit of the TEST1 register is set to a
“0”, then the data may be transmitted at any time following
the vertical sync.
The data consists of a stream of 9 bytes. In normal use it is
expected that the first eight bytes will be data, and the
remaining byte will be used as a checksum.Alternatively, the
ninth byte may be used as an additional data byte.
Another video channel provides a clock pulse stream of
exactly 72 pulses. The logic counts the number of pulses
between two horizontal sync pulses.
If the number of clock
pulses is greater or less than 72, then the data is ignored.
If
the count is 72, then the data is shifted into registers 2E-36
upon arrival of the next horizontal sync, provided the output
20063521
FIGURE 4. Timing Intervals with WCHE = 1
20063522
FIGURE 5. Timing Intervals with WCHE = 0
L
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