參數(shù)資料
型號: LM1270
廠商: National Semiconductor Corporation
英文描述: Hi-Brite 200 MHz I2C Compatible RGB Image Enhancer with Video Auto Sizing
中文描述: 高亮度場致200兆赫與I2C兼容的RGB視頻自動上漿圖像增強
文件頁數(shù): 17/27頁
文件大?。?/td> 1302K
代理商: LM1270
Microcontroller Interface
The microcontroller interfaces to the LM1270 pre-amp via an
I
C compatible interface. The protocol of the interface begins
with the Start Pulse followed by a byte comprised of a
seven-bit Slave Device Address and a Read/Write bit as the
LSB. Therefore the address of the LM1270 for writing is 54h
(0101 0100) and the address for reading is 55h (0101 0101).
Figures 13, 14
show a write and read sequence across the
I
2
C compatible interface.
WRITE SEQUENCE
The write sequence begins with a start condition which
consists of the master pulling SDA low while SCL is held
high. The slave device address is sent next. The address
byte is made up of an address of seven bits (7–1) and the
read/write bit (0). Bit 0 is low to indicate a write operation.
Each byte that is sent is followed by an acknowledge. When
SCL is high the master will release the SDA line. The slave
must pull SDA low to acknowledge. The address of the
register to be written to is sent next. Following the register
address and the acknowledge bit the data for the register is
sent. If bit 0 of register 0Ah is set low (default value) then the
LM1270 is set for the increment mode. In this mode when
more than one data byte is sent it is automatically incre-
mented into the next address location. See
Figure 13
. Note
that each data byte is followed by an acknowledge bit.
READ SEQUENCE
Read sequences are comprised of two I
2
C compatible trans-
fer sequences: The first is a write sequence that only trans-
fers the address to be accessed. The second is a read
sequence that starts at the address transferred in the previ-
ous address write access and incrementing to the next ad-
dress upon every data byte read. This is shown in
Figure 14
.
The write sequence consists of the Start Pulse, the Slave
Device Address including the Read/Write bit (a zero, indicat-
ing a write), then its Acknowledge bit. The next byte is the
address to be accessed, followed by itsAcknowledge bit and
the Stop bit indicating the end of the address only write
access.
Next the read data access is performed beginning with the
Start Pulse, the Slave Device Address including the Read/
Write bit (a one, indicating a read) and the Acknowledge bit.
The next 8 bits will be the data read from the address
indicated by the write sequence. Subsequent read data
bytes will correspond to the next increment address loca-
tions. Each data byte is separated from the other data bytes
by an Acknowledge bit.
20063531
FIGURE 13. I
2
C Compatible Write Sequence
L
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