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參數(shù)資料
| 型號： | LM1247 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 150 MHz I2C Compatible RGB Preamplifier with Internal 512 Character OSD ROM, 512 Character RAM and 4 DACs |
| 中文描述： | 150 MHz的I2C兼容的RGB前置放大器512個字符OSD光盤，512個字符RAM和4 DAC的內(nèi)置 |
| 文件頁數(shù)： | 5/48頁 |
| 文件大小： | 3141K |
| 代理商： | LM1247 |
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System Interface Signal Characteristics
(Continued)
Note 1:
Limits of Absolute Maximum Ratings indicate below which damage to the device must not occur.
Note 2:
Operating ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits.
Note 3:
All voltages are measured with respect to GND, unless otherwise specified.
Note 4:
Human body model, 100 pF discharged through a 1.5 k
resistor.
Note 5:
Input from signal generator: t
r
, t
f
<
1 ns.
Note 6:
Typical specifications are specified at +25C and represent the most likely parametric norm.
Note 7:
Datasheet min/max specification limits are guaranteed by design, test, or statistical analysis. The guaranteed specifications apply only for the test conditions
listed. Some performance characteristics may change when the device is not operated under the listed test conditions.
Note 8:
The supply current specified is the quiescent current for V
CC
and 5V Dig with R
L
=
∞
. Load resistors are not required and are not used in the test circuit,
therefore all the supply current is used by the pre-amp.
Note 9:
Linearity Error is the maximum variation in step height of a 16 step staircase input signal waveform with a 0.7 V
P-P
level at the input. All 16 steps equal,
with each at least 100 ns in duration.
Note 10:
dt/dV
CC
= 200
*
(t
5.5V
–t
4.5V
)/ ((t
5.5V
+ t
4.5V
)) %/V, where: t
5.5V
is the rise or fall time at V
CC
= 5.5V, and t
4.5V
is the rise or fall time at V
CC
= 4.5V.
Note 11:
A
track is a measure of the ability of any two amplifiers to track each other and quantifies the matching of the three gain stages. It is the difference in
gain change between any two amplifiers with the contrast set to A
C50% and measured relative to the A
max condition. For example, at A
max the three
amplifiers’ gains might be 12.1 dB, 11.9 dB, and 11.8 dB and change to 2.2 dB, 1.9 dB and 1.7 dB respectively for contrast set to A
V
C50%. This yields a typical
gain change of 10.0 dB with a tracking change of
±
0.2 dB.
Note 12:
The ABL input provides smooth decrease in gain over the operational range of 0 dB to 5 dB:
A
= A(V
ABL
= V
ABL MAX GAIN
) – A (V
ABL
=
V
ABL MIN GAIN
). Beyond 5 dB the gain characteristics, linearity and pulse response may depart from normal values.
Note 13:
Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200 pF cap is charged to the specific voltage, then discharged directly into the
IC with no external series resistor (resistance of discharge path must be under 50
).
Note 14:
Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation. Terminate the undriven amplifier
inputs to simulate generator loading. Repeat test at f
IN
= 10 MHz for V
SEP
10 MHz.
Note 15:
A minimum pulse width of 200 ns is the guaranteed minimum for a horizontal line of 15 kHz. This limit is guaranteed by design. If a lower line rate is used
then a longer clamp pulse may be required.
Note 16:
Adjust input frequency from 10 MHz (A
V
max reference level) to the 3 dB corner frequency (f
3 dB
).
Note 17:
Once the spot killer has been activated, the LM1247 remains in the off state until V
CC
is cycled (reduced below 0.5V and then restored to 5V).
Hexadecimal and Binary Notation
Hexadecimal numbers appear frequently throughout this
document, representing slave and register addresses, and
register values. These appear in the format “0x...”. For ex-
ample, the slave address for writing the registers of the
LM1247 is hexadecimal BA, written as 0xBA. On the other
hand, binary values, where the individual bit values are
shown, are indicated by a trailing “b”. For example, 0xBA is
equal to 10111010b. A subset of bits within a register is
referred to by the bit numbers in brackets following the
register value. For example, the OSD contrast bits are the
fourth and fifth bits of register 0x8438. Since the first bit is bit
0, the OSD contrast register is 0x8438[4:3].
Register Test Settings
Table 1
shows the definitions of the Test Settings 1–8 re-
ferred to in the specifications sections. Each test setting is a
combination of five hexadecimal register values, Contrast,
Gain (Blue, Red, Green) and DC offset.
TABLE 1. Test Settings
Control
No. of Bits
Test Settings
4
0x7F
(Max)
Set V
O
to
2 V
P-P
0x05
1
2
3
5
6
7
8
Contrast
7
0x7F
(Max)
0x7F
(Max)
0x00
(Min)
0x00
Min
0x7F
(Max)
0x05
0x7F
(Max)
0x7F
(Max)
0x07
(Max)
0x40
(50.4%)
0x7F
(Max)
0x05
0x7F
(Max)
0x40
(50.4%)
0x05
0x7F
(Max)
0x00
(Min)
0x05
0x7F
(Max)
0x7F
(Max)
0x05
B, R, G
Gain
DC Offset
7
3
L
www.national.com
5
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