Circuit Description
(Continued)
Figure 7 also shows how the contrast control circuit is con-
figured. Resistors R23, 24, diodes D3, 4 and transistor Q13
are used to establish a low impedance zero TC half supply
voltage reference at the base of Q14. The differential ampli-
fier formed by Q15, 16 and feedback transistor Q17 along
with resistors R27, 28 establish a diferential base voltage
for Q3 and Q4 in Figure 6. When externally adding or sub-
tracting current from the collector of Q16, a new differential
voltage is generated that reflects the change in the ratio of
currents in Q15 and Q16. To provide voltage control of the
Q16 current, resistor R29 is added between the Q16 collec-
tor and pin 12. A capacitor should be added from pin 12 to
ground to prevent noise from the contrast control pot from
entering the IC.
Figure 8 is a simplified schematic of the clamp gate and
clamp comparator sections of the LM1203. The clamp gate
circuit consists of a PNP input buffer transistor (Q18), a PNP
emitter coupled pair referenced on one side to 2.1V (Q19,
20) and an output switch (Q21). When the clamp gate input
at pin 14 is high (
l
1.5V) the Q21 switch is on and shunts
the I1 850
m
A current to ground. When pin 14 is low (
k
1.3V)
the Q21 switch is off and the I1 850
m
A current source is
mirrored or ‘‘turned around’’ by reference diode D5 and Q26
to provide a 850
m
A current source for the clamp compara-
tor(s). The inputs to the comparator are similar to the clamp
gate input except that an NPN emitter coupled pair is used
to control the current which will charge or discharge the
clamp capacitors at pins 5, 8, or 10. PNP transistors are
used at the inputs because they offer a number of advan-
tages over NPNs. PNPs will operate with base voltages at or
near ground and will usually have a greater reverse emitter
base breakdown voltage (BVebo). Because the differential
input voltage to the clamp comparator during the video scan
period could be greater than the BVebo of NPN transistors a
resistor (R34) with a value one half that of R33 or R35 is
connected between the bases of Q23 and Q27. This resis-
tor will limit the maximum differential input to Q24, 25 to
approximately 350 mV. The clamp comparator common
mode range is from ground to approximately 9V and the
maximum differential input voltage is V
CC
and ground.
TL/H/9178–8
FIGURE 8. Simplified Schematic of LM1203 Clamp Gate and Clamp Comparator Circuits
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