參數(shù)資料
型號: LIS2L02AS4
廠商: STMICROELECTRONICS
元件分類: 模擬信號調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PDSO24
封裝: SO-24
文件頁數(shù): 5/7頁
文件大小: 454K
代理商: LIS2L02AS4
5/7
LIS2L02AS4
Figure 1. Equivalent electrical circuit
The complete signal processing uses a fully differential structure, while the final stage converts the differential
signal into a single-ended one to be compatible with the external world.
The first stage is a low-noise capacitive amplifier that implements a Correlated Double Sampling (CDS) at its
output to cancel the offset and the 1/f noise. The produced signal is then sent to two different S&Hs, one for
each channel, and made available to the outside.
The low noise input amplifier operates at 200 kHz while the two S&Hs operate at a sampling frequency of 66
kHz. This allows a large oversampling ratio, which leads to in-band noise reduction and to an accurate output
waveform.
All the analog parameters (output offset voltage and sensitivity) are ratiometric to the voltage supply: increasing
or decreasing the voltage supply, the sensitivity and the offset will increase or decrease accordingly. This fea-
ture provides the cancellation of the error related to the voltage supply along an analog to digital conversion
chain.
1.2 Factory calibration
The IC interface is factory calibrated to provide to the final user a device ready to operate. The parameters which
are trimmed are: gain, offset, common mode and internal clock frequency.
The trimming values are stored inside the device by a non volatile structure. Any time the device is turned on,
the trimming parameters are downloaded into the registers to be employed during the normal operation thus
allowing the final user to employ the device without any need for further calibration
Cs1x
Cs2x
Cps1
Cps2
Cpr
Rs2
Rs1
Rr
S1x
rot
S2x
Cs1y
Cs2y
Cps1
Cps2
Cpr
Rs2
Rs1
Rr
S1y
S2y
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