- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄358795 > LH521028 (Sharp Corporation) CMOS 64K x 18 Static RAM PDF資料下載
參數(shù)資料
| 型號： | LH521028 |
| 廠商： | Sharp Corporation |
| 英文描述： | CMOS 64K x 18 Static RAM |
| 中文描述： | 64K的× 18的CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 4/15頁 |
| 文件大小： | 153K |
| 代理商： | LH521028 |
PIN DEFINITIONS
V
CC
Positive Supply Voltage Terminals
V
SS
Reference Terminals
A
0
– A
15
The Address bus is decoded to select one 18-bit word
out of the total 64K words for Read and Write operations.
Address Bus
Input
E
Chip Enable
Active LOW Input
Chip Enable is used to enable the device for Read and
Write operations. When HIGH, both Read and Write
operations are disabled and the device is in a reduced
power state. When LOW, a Read or Write operation is
enabled.
W
Write Enable
Active LOW Input
Write Enable is used to select either Read or Write
operations when the device is enabled. When Write
Enable is HIGH and the device is Enabled, a Read
operation is selected. When Write Enable is LOW and the
device is enabled, a Write operation is selected. A Byte-
write operation is available by using the Byte-select con-
trols.
S
H
, S
L
Select High
Select Low
Active LOW Inputs
The Select High and Select Low signals, in conjunction
with the Chip Enable and Write Enable signals, allow the
selection of the individual bytes for Read and Write op-
erations. When High, the Select signal will deselect its
byte and prevent Read or Write operations. When the
Select signal is LOW and Chip Enable is LOW, a Read or
Write operation is performed at the location determined
by the contents of the Address bus. When Chip Enable is
HIGH, the Select signals are Don’t Care. Select Low (S
L
)
is assigned to DQ
0
– DQ
8
and Select High (S
H
) is
assigned to DQ
9
– DQ
17
.
ALE
Address Latch
Enable
Active High Input
The Address Latch Enable signal is used to control the
Transparent latches on the Address bus. The Latches are
transparent when HIGH and are latched when LOW. If
not required, Address Latch Enable may be tied HIGH,
leaving the Address bus in a transparent condition.
DQ
0
– DQ
17
Data Bus
DQ
0
– DQ
8
comprise the Low byte, selected by S
L
,
and DQ
9
– DQ
17
comprise the High Data byte, selected
by S
H
. The Data Bus is in a high impedance input mode
during Write operations and standby. The Data bus is in
a low-impedance output mode during Read operations.
Input/Output
G
Output Enable
Active LOW Input
The Output Enable signal is used to control the output
buffers on the Data Input/Output bus. When G is HIGH,
all output buffers are forced to a high impedance condi-
tion. When G is LOW, the output buffers will become
active only during a Read operation (E and S
H
/ S
L
are
LOW, W is HIGH).
LH521028
CMOS 64K
×
18 Static RAM
4-214
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LH52253K35 | CMOS 64K X 4 STATIC RAM |
| LH52256C-10LL | CMOS 256K (32K x8) Static RAM(CMOS 256K (32K x8) 靜態(tài)RAM) |
| LH52256CD-70LL | CMOS 256K (32K x8) Static RAM(CMOS 256K (32K x8) 靜態(tài)RAM) |
| LH52256CHN-70LL | CMOS 256K (32K x8) Static RAM(CMOS 256K (32K x8) 靜態(tài)RAM) |
| LH52256CHN-85LL | 256K SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH521028A | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:CMOS 64K x 18 Static RAM |
| LH521028AU-15 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 SRAM |
| LH521028AU-17 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 SRAM |
| LH521028AU-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 SRAM |
| LH521028AU-25 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x18 SRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。