Min. Delay of Clock to ddr_dq_in flops = t
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� LFXP15E-3F484C
寤犲晢锛� Lattice Semiconductor Corporation
鏂囦欢闋佹暩(sh霉)锛� 295/397闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 15.4KLUTS 300I/O 484-BGA
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绯诲垪锛� XP
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 15000
RAM 浣嶇附瑷�(j矛)锛� 331776
杓稿叆/杓稿嚭鏁�(sh霉)锛� 300
闆绘簮闆诲锛� 1.14 V ~ 1.26 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 85°C
灏佽/澶栨锛� 484-BBGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 484-FPBGA锛�23x23锛�
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Board Timing Guidelines
Lattice Semiconductor
for the DDR SDRAM Controller IP Core
17-4
Min. Delay of Clock to ddr_dq_in flops = tFPGA_CLK (min) + tSKEW + tFDH
To meet hold time at ddr_dq_in flops, Data Delay - Clock Delay > 0
Therefore:
tDDR_CLK (min) + tBDC + tAC (min) + tBDD + tPD - tFPGA_CLK (min) - tSKEW - tFDH > 0
Isolating the board delays, we get:
(tBDD + tBDC) > tFPGA_CLK (min) + tSKEW + tFDH - tDDR_CLK (min) - tAC (min) - tPD
(tBDD + tBDC) > (1.239) ns + 0.3 + (-1.609ns) - (1.138) - (-0.75) - 0
(tBDD + tBDC) > -0.458 ns
Conclusion: To meet read set-up and hold timing, board delay for ddr_dq, ddr_clk and ddr_clk_n should be:
-0.458ns < (tBDD + tBDC) < -0.03ns
Write Operation
For a proper write operation, data (ddr_dq) should meet set-up (tDS) and hold (tDH) time requirements of DDR
SDRAM with respect to ddr_dqs signal. The ddr_dqs signal is generated with respect to negative edge of
pll_nclk
and data ddr_dq out is generated with respect to positive edge of pll_nclk as shown in Figure 17-3.
As a result, 1/2 clk2x (3.75ns/2) is provided as set-up and hold for ddr_dq_out with respect to dqs_out.
For maximum set-up and hold margin, the ddr_dqs and ddr_dq traces on the board should be matched.
Table 17-2. Write Operation Timing Arcs
Figure 17-3. Write Timing Diagram
Write Set-up
Clock Delay = tCDQS + 1/2 clk2x - tDS + tBDDS
Data Delay = tCDQ + tBDD
Symbol
Description
ORCA 4
tDS
Set-up time required by the DQ with respect to DQS for DDR SDRAM.
0.75ns
tDH
Hold time required by the DQ with respect to DQS for DDR SDRAM.
0.75 ns
tCDQ
Clock-to-out timing for ddr_dq with respect to pll_nclk.鈥�
tCDQS
Clock-to-out timing for ddr_dqs with respect to pll_nclk.鈥�
tBDDS
Board delay of ddr_dqs from FPGA to DDR SDRAM pins.
鈥�
pll_nclk (clk2x)
dqs_out
ddr_dq_out
t
CDQS
t
CDQ
鐩搁棞(gu膩n)PDF璩囨枡
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LFXP15C-3F484C IC FPGA 15.5KLUTS 300I/O 484-BGA
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ACM36DTAH CONN EDGECARD 72POS R/A .156 SLD
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鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
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