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LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysCLOCK PLL Design and Usage Guide
11-16
DCS MODE = NEG
At the falling edge (NEG) of SEL, the DCSOUT changes from CLK0 to CLK1.
DCS MODE = HIGH_LOW
SEL is active high (HIGH) to select CLK1, and the disabled output is LOW.
DCS MODE = LOW_LOW
SEL is active low (LOW) to select CLK0, and the disabled output is LOW.
DCS MODE = HIGH_HIGH
SEL is active high (HIGH) to select CLK1, and the disabled output is HIGH.
DCS MODE = LOW_HIGH
SEL is active low (LOW) to select CLK0, and the disabled output is HIGH.
CLK0
CLK1
SEL
DCSOUT
SEL Falling edge:
- Wait for CLK1 falling edge,
latch output & remain low
- Switch output at CLK0 falling edge
SEL Rising edge:
- Wait for CLK0 falling edge,
latch output & remain low
- Switch output at CLK1 falling edge
DCS MODE = NEG
CLK1
SEL
DCSOUT
- Switch low at CLK1 falling edge.
- If SEL is low, output stays low at on
CLK1 rising edge. SEL must not
change during setup prior to rising clock.
DCS MODE = HIGH_LOW
CLK0
SEL
DCSOUT
- Switch low at CLK0 falling edge.
- If SEL is high, output stays low at
on CLK0 rising edge.
DCS MODE = LOW_LOW