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參數(shù)資料
| 型號： | LFXP15C-4F484C |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 234/397頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 15.5KLUTS 300I/O 484-BGA |
| 標(biāo)準(zhǔn)包裝： | 60 |
| 系列： | XP |
| 邏輯元件/單元數(shù)： | 15000 |
| RAM 位總計： | 331776 |
| 輸入/輸出數(shù)： | 300 |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 484-BBGA |
| 供應(yīng)商設(shè)備封裝： | 484-FPBGA（23x23） |
13-10
Lattice Semiconductor
LatticeXP sysCONFIG Usage Guide
Table 13-7. Configuration Modes for the LatticeXP
Configuration Options
Several configuration options are available for each CONFIG_MODE.
When daisy chaining multiple FPGA devices a configuration overflow option is provided. Configuration data over-
flow occurs once the first FPGA has completed its download, the remaining data in the configuration storage
device is then output through the first FPGA to subsequent FPGAs. Configuration data overflow is not supported
when using SDM.
When using a master clock, the master clock frequency can be set.
A security bit is provided to prevent SRAM or Flash readback.
By setting the proper parameters in the Lattice ispLEVER design software the selected configuration options are
set in the generated bitstream. As the bitstream is loaded into the device the selected configuration options take
effect. These options are described in the following sections.
Bypass Overflow Option
The Bypass overflow option can be used in serial and parallel device daisy chains. When the first device has com-
pleted configuration data download, and the Bypass option preference is selected, data coming into the device
configuration port on the sysCONFIG pins will overflow serially out of DOUT and into the DIN pin of the next slave
serial device. The Bypass option is selected in ispLEVER by right-clicking on Generate Bitstream Data and clicking
on Properties.
In serial configuration mode, once all of the configuration data has been loaded into the first device, the Bypass
option connects the DIN pin to DOUT pin via a bypass register. The bypass register is initialized with a ‘1’ at the
beginning of configuration.
In parallel configuration mode, once all of the configuration data has been loaded into the first device, the Bypass
option causes the data coming from D[0:7] to be serially shifted to DOUT. The serialized data is shifted to DOUT
through the bypass register. D[0] of the byte wide data will be shifted out first followed by D[1], D[2] and so on.
Once the Bypass option starts, the device will remain in Bypass until the wake up sequence completes.
Flow-Though Overflow Option
The Flow-Through overflow option is used in parallel mode only. The Flow-Through option causes the CSON pin to
go low when the FPGA has received all of its configuration data, driving the chip select on the next device in the
daisy chain so that it will start reading configuration data from D[0:7]. The Flow Through Option will also tri-state
Configuration Mode
CFG[1] CFG[0]
CONFIG_MODE
1
Chain Mode
2
Slave Serial (no overload option)
0
Slave_Serial
Disable
Slave Serial (Bypass ON)
0
Slave_Serial
Bypass
Master Serial (no overload option)
0
1
Master_Serial
Disable
Master Serial (Bypass ON)
0
1
Master_Serial
Bypass
Slave Parallel (no overload option)
1
0
Slave_Parallel
Disable
Slave Parallel (Bypass ON)
1
0
Slave_Parallel
Bypass
Slave Parallel (Flow Through ON)
1
0
Slave_Parallel
Flowthrough
Self Download Mode (SDM)
1
None/Slave_Parallel
4
Disable
ispJTAG (1149.1 interface)
X
3
X
3
None
5
1. CONFIG_MODE can be found in the ispLEVER Preference Editor.
2. CHAIN_MODE can be found in the ispLEVER bitgen options (right-click on Generate Bitstream Data and click on Properties).
3. The ispJTAG interface is always on.
4. If ispJTAG is used exclusively to access the on-chip Flash and SRAM select None, if Slave Parallel is used to access the Flash and/or the
SRAM select Slave_Parallel.
5. The None selection indicates that no dual-purpose pins are reserved for configuration. This is the default.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| LFXP15C-4F484I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 15.4K LUTs 1.8/2.5/3 .3V -4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFXP15C-4FN256C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 15.4K LUTs 188 IO 1. 8/2.5/3.3V -4 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFXP15C-4FN256I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 15.4K LUTs 188 IO 1. 8/2.5/3.3V-4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFXP15C-4FN388C | 功能描述:FPGA - 現(xiàn)場可編程門陣列 15.4K LUTs 268 IO 1. 8/2.5/3.3V -4 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| LFXP15C-4FN388I | 功能描述:FPGA - 現(xiàn)場可編程門陣列 15.4K LUTs 268 IO 1. 8/2.5/3.3V-4 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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