參數(shù)資料
型號： LFX125EB-03FN256C
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 71/119頁
文件大小： 0K
描述： IC FPGA 139K GATES 256-BGA
標準包裝： 90
系列： ispXPGA®
邏輯元件/單元數(shù)： 1936
RAM 位總計： 94208
輸入/輸出數(shù)： 160
門數(shù)： 139000
電源電壓： 2.3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 256-BGA
供應商設備封裝： 256-FPBGA（17x17）
Lattice Semiconductor
ispXPGA Family Data Sheet
51
sysHSI Block Timing
Figure 24 provides a graphical representation of the SERDES receiver input requirements. It provides guidance on
a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and P and N
input skew tolerance.
Figure 24. Receive Data Eye Diagram Template (Differential)
The data pattern eye opening at the receive end of a link is considered the ultimate measure of received signal
quality. Almost all detrimental characteristics of a transmit signal and the interconnection link design result in eye
closure. This combined with the eye-opening limitations of the line receiver can provide a good indication of a link’s
ability to transfer error-free data.
Signal jitter is of special interest to system designers. It is often the primary limiting characteristic of long digital
links and of systems with high noise level environments. An interesting characteristic of the clock and data recovery
(CDR) portion of the ispXPGA SERDES receiver is its ability to filter incoming signal jitter that is below the clock
recovery PLL bandwidth. For signals with high levels of low frequency jitter, the receiver can detect incoming data
error free, with eye openings significantly less than that shown in Figure 24.
eo
SIN
V
THD
200 mV Differential
+/- 100 mV Single Ended
jt
TH
Bit Time
jt
TH : Optimum Threshold Crossing Jitter
jt
TH
SELECT
DEVICES
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相關代理商/技術參數(shù)
參數(shù)描述
LFX125EB-03FN256I 功能描述:FPGA - 現(xiàn)場可編程門陣列 E-Ser139K Gt ispJTAG 2.5/3.3V -3 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFX125EB-03FN516C 功能描述:FPGA - 現(xiàn)場可編程門陣列 E-Ser139K Gt ispJTA G 2.5/3.3V -3 Spd RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFX125EB-03FN516I 功能描述:FPGA - 現(xiàn)場可編程門陣列 E-Ser139K Gt ispJTA G 2.5/3.3V -3 Spd I RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFX125EB-04F256C 功能描述:FPGA - 現(xiàn)場可編程門陣列 139K Gates, 160 I/O 2.5/3.3V, -4 speed RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
LFX125EB-04F256I 功能描述:FPGA - 現(xiàn)場可編程門陣列 139K Gates, 160 I/O 2.5/3.3V, -4 speed RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256
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