Figure 3-14. sysCONFIG Master Serial Port Timing Figure 3-15. sysCONFI" />
參數(shù)資料
型號: LFEC20E-5FN672C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 124/163頁
文件大?。?/td> 0K
描述: IC FPGA 19.7KLUTS 672FPBGA
標(biāo)準(zhǔn)包裝: 40
系列: EC
邏輯元件/單元數(shù): 19700
RAM 位總計: 434176
輸入/輸出數(shù): 400
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 672-BBGA
供應(yīng)商設(shè)備封裝: 672-FPBGA(27x27)
3-27
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Figure 3-14. sysCONFIG Master Serial Port Timing
Figure 3-15. sysCONFIG Slave Serial Port Timing
Figure 3-16. Power-On-Reset (POR) Timing
CCLK (output)
DIN
DOUT
t
SUMCDI
t
HMCDI
t
CODO
CCLK (input)
DIN
DOUT
t
SUSCDI
t
HSCDI
t
CODO
t
SSCL
t
SSCH
CCLK
2
DONE
VCC/VCCAUX
1
CFG[2:0]
3
t
ICFG
Valid
INITN
t
VMC
t
SUCFG
t
HCFG
1. Time taken from VCC or VCCAUX, whichever is the last to reach its VMIN.
2. Device is in a Master Mode.
3. The CFG pins are normally static (hard wired).
相關(guān)PDF資料
PDF描述
HSC50DREH-S734 CONN EDGECARD 100POS .100 EYELET
LFECP20E-4FN484I IC FPGA 19.7KLUTS 484FPBGA
FMC12DREF-S734 CONN EDGECARD 24POS .100 EYELET
ABB40DHAN CONN EDGECARD 80POS R/A .050 SLD
ABB40DHAD CONN EDGECARD 80POS R/A .050 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LFEC20E-5FN672I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC20E-5Q208C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC20E-5Q208I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC20E-5QN208C 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet
LFEC20E-5QN208I 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:LatticeECP/EC Family Data Sheet