Table 2-5. PLL Signal Descriptions For more information about the PLL, please see the list of" />
參數資料
型號: LFEC10E-5QN208C
廠商: Lattice Semiconductor Corporation
文件頁數: 46/163頁
文件大?。?/td> 0K
描述: IC FPGA 10.2KLUTS 147I/O 208QFP
標準包裝: 24
系列: EC
邏輯元件/單元數: 10200
RAM 位總計: 282624
輸入/輸出數: 147
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 208-BFQFP
供應商設備封裝: 208-PQFP(28x28)
2-11
Architecture
LatticeECP/EC Family Data Sheet
Table 2-5. PLL Signal Descriptions
For more information about the PLL, please see the list of technical documentation at the end of this data sheet.
Dynamic Clock Select (DCS)
The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and
outputs a clock signal without any glitches or runt pulses. This is achieved regardless of where the select signal is
toggled. There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-13 illustrates
the DCS Block Macro.
Figure 2-13. DCS Block Primitive
Figure 2-14 shows timing waveforms of the default DCS operating mode. The DCS block can be programmed to
other modes. For more information about the DCS, please see the list of technical documentation at the end of this
data sheet.
Signal
I/O
Description
CLKI
I
Clock input from external pin or routing
CLKFB
I
PLL feedback input from CLKOP (PLL internal), from clock net (CLKOP) or from a user clock
(PIN or logic)
RST
I
“1” to reset PLL
CLKOS
O
PLL output clock to clock tree (phase shifted/duty cycle changed)
CLKOP
O
PLL output clock to clock tree (No phase shift)
CLKOK
O
PLL output to clock tree through secondary clock divider
LOCK
O
“1” indicates PLL LOCK to CLKI
DDAMODE
I
Dynamic Delay Enable. “1”: Pin control (dynamic), “0”: Fuse Control (static)
DDAIZR
I
Dynamic Delay Zero. “1”: delay = 0, “0”: delay = on
DDAILAG
I
Dynamic Delay Lag/Lead. “1”: Lead, “0”: Lag
DDAIDEL[2:0]
I
Dynamic Delay Input
DDAOZR
O
Dynamic Delay Zero Output
DDAOLAG
O
Dynamic Delay Lag/Lead Output
DDAODEL[2:0]
O
Dynamic Delay Output
DCS
CLK0
DCSOUT
CLK1
SEL
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