參數(shù)資料
型號: LFEC10E-3QN208I
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 127/163頁
文件大?。?/td> 0K
描述: IC FPGA 10.2KLUTS 208PQFP
標(biāo)準(zhǔn)包裝: 24
系列: EC
邏輯元件/單元數(shù): 10200
RAM 位總計: 282624
輸入/輸出數(shù): 147
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
3-30
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Switching Test Conditions
Figure 3-21 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,
voltage, and other test conditions are shown in Table 3-6.
Figure 3-21. Output Test Load, LVTTL and LVCMOS Standards
Table 3-6. Test Fixture Required Components, Non-Terminated Interfaces
Test Condition
R1
CL
Timing Ref.
VT
LVTTL and other LVCMOS settings (L -> H, H -> L)
0pF
LVCMOS 3.3 = 1.5V
LVCMOS 2.5 = VCCIO/2
LVCMOS 1.8 = VCCIO/2
LVCMOS 1.5 = VCCIO/2
LVCMOS 1.2 = VCCIO/2
LVCMOS 2.5 I/O (Z -> H)
188
0pF
VCCIO/2
VOL
LVCMOS 2.5 I/O (Z -> L)
VCCIO/2
VOH
LVCMOS 2.5 I/O (H -> Z)
VOH - 0.15
VOL
LVCMOS 2.5 I/O (L -> Z)
VOL + 0.15
VOH
Note: Output test conditions for all other interfaces are determined by the respective standards.
DUT
VT
R1
CL*
Test Point
*CL Includes Test Fixture and Probe Capacitance
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