參數(shù)資料
型號: LFC789D25CPW
廠商: Texas Instruments, Inc.
英文描述: DUAL LINEAR FET CONTROLLER
中文描述: 雙線場效應(yīng)管控制器
文件頁數(shù): 6/11頁
文件大?。?/td> 218K
代理商: LFC789D25CPW
SLLS565B MARCH 2003 REVISED SEPTEMBER 2004
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
MOSFET SELECTION: BENEFITS OF NMOS PASS ELEMENTS REVISITED
A great benefit of having an external pass element is that the control circuitry can be powered by a separate
supply (V
CC
), other
than the one used as the input to the pass element (V
PWR
). This feature allows the use of
an NMOS pass element, which requires a positive V
GS
>
V
T
for operation. With a separate V
CC
pin to the
controller, the voltage at the gate of the NMOS readily can exceed the voltage at the drain; thus, V
GS
easily
can
exceed V
DS
+ V
T
, allowing the NMOS to operate in the triode region (V
DS
V
GS
V
T
). In the triode region, V
DS
can be very small, thus achieving very low dropout.
The external NMOS selected for the pass transistor has significant impact on the overall characteristics of the
regulator, as discussed in the following paragraphs.
Maximum output current
A benefit of an external pass element is that the designer can size the NMOS to easily sustain the maximum
I
OUT
expected. This allows great flexibility, along with cost and space savings, because each regulator has its
pass element tailored to its individual needs. In addition, using an NMOS pass element allows for smaller size
(and subsequently, lower cost) than a PMOS element for the same current-carrying ability.
Dropout
Choosing an NMOS with very low R
DS(on)
characteristics provides the regulator with very low dropout because
dropout will be
I
OUT
×
R
DS(on)
. This lower dropout also results in better efficiency and lower heat dissipation
in the pass element for a given I
OUT
.
Maximum programmable output voltage and NMOS threshold voltage, V
T
The maximum output voltage that can be regulated by the programmable regulator depends on the device’s
power supply (V
CC
) and threshold voltage (V
T
) of the NMOS. With the drive voltage tied to the gate and V
OUT
connected to the source of the NMOS, a minimum V
GS
= V
T
must be maintained in order to maintain the
n-channel inversion layer. The maximum V
OUT
is calculated as follows:
V
OUT
= V
S
= V
G
V
T
With V
CC
= 12 V and a corresponding worst-case gate drive voltage of 9 V, the highest achievable
V
OUT
= 9 V V
T
.
Stability
A quality of the old npn regulators was their inherent stability under almost any type of load conditions and output
capacitors.
An
NMOS
regulator
has
the
same
equivalent-series-resistance (ESR) values are not needed for stability, but still should be chosen properly for
best transient response (see below).
benefit.
Thus,
capacitor
selection
and
capacitor selection
C
out
: Although a minimum capacitance is not needed for stability with an NMOS pass device, higher capacitance
values improve transient response. In addition, low-ESR capacitors also help transient response. Tantalum or
aluminum electrolytics can be used for bulk capacitances, while ceramic bypass capacitors can be used to
decouple high-frequency transients due to their low ESL (equivalent series inductance).
C
in
: Input capacitors placed at the drain of the NMOS pass transistor (V
PWR
) help improve the overall transient
response by suppressing surges in V
PWR
during fast load changes. Low-ESR tantalum or aluminum electrolytic
capacitors can be used; higher capacitance values improve transient response. A 0.1-
μ
F ceramic capacitor can
be placed at the V
CC
pin of the LFC789D25 to provide bypassing.
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