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參數(shù)資料
| 型號： | LF6197 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 運動控制電子 |
| 英文描述： | 160 ns Monolithic Sample-and-Hold Amplifier |
| 中文描述： | 160納秒單片采樣保持放大器 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 214K |
| 代理商： | LF6197 |
Application Hints
1.0 LOGIC CONFIGURATIONS
The LF6197 can be configured to interface with TTL,
CMOS, or ECL logic. The device is configured for the de-
sired logic using the two Logic Reference pins (LR1 and
LR2).
1.1 TTL Logic
To configure the device to operate with TTL logic, the LR1
pin should be left open and the LR2 pin should be grounded
(Figure 4). This will set the threshold of the logic comparator
at 1.4V.
1.2 CMOS Logic
To configure the device to operate with CMOS logic (with a
2.5V threshold at the comparator), several options are avail-
able. The LR1 and LR2 pins can be tied together and con-
nected to a 2.5V reference (Figure 5); or LR2 can be set to
1.1V with a resistor diode network and LR1 can be by-
passed to ground with a 0.01
m
F capacitor (Figure 6).
1.3 ECL Logic
To operate with ECL logic (threshold at
b
1.3V), set LR2 at
b
2.7V with a voltage divider from the negative supply and
bypass LR1 with a 0.01
m
F capacitor (Figure 7).
2.0 ZENER REFERENCE OUTPUT
The LF6197 includes an internal zener diode to bias various
sections of the chip. The zener diode output is brought out
at pin 14; the voltage at this pin is typically 6.25V when the
device is powered from
g
15V supplies. For optimum device
performance, pin 14 must be bypassed to ground with a
0.01
m
F capacitor. If the device is powered from
g
5V sup-
plies, then pin 14 must be biased at 2.5V from a low imped-
ance source (Figure 3).
TL/H/11381–6
FIGURE 3. Biasing Pin 14 to 2.5V
for Operation from
g
5V Supplies
3.0 ADJUSTING GAIN
The LF6197 allows the user to amplify as well as to sample-
and-hold an input signal. This feature eliminates the need
for an amplifier preceding the S/H amplifier in many appli-
cations. Familiar op-amp feedback topologies are employed
to configure the LF6197 for non-inverting (Figure 8) or in-
verting (Figure 9) gains. Note that a feedback resistor of
value 1 k
X
or larger must be used for all gain settings, in-
cluding non-inverting unity gain. The feedback resistor is re-
quired to limit the current through LF6197’s internal clamp
diodes when the device is in the hold mode.
4.0 POWER SUPPLY SEQUENCING
When power supply to the LF6197 is turned on, the nega-
tive supply must come on before the positive supply. Mean-
while, when the power supply is turned off, the positive sup-
ply must turn off before the negative supply. Improper power
supply sequencing may destroy the device. To protect the
device against improper power supply sequencing, anti-re-
versal diodes may be used across the supply pins
(Figure 10).
TL/H/11381–7
Threshold
e
1.4V
FIGURE 4. TTL Logic
TL/H/11381–8
Threshold
e
2.5V
FIGURE 5. CMOS Logic
9
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