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參數(shù)資料
| 型號(hào)： | LF412ACN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 運(yùn)算放大器 |
| 英文描述： | Low Offset, Low Drift Dual JFET Input Operational Amplifier |
| 中文描述： | DUAL OP-AMP, 1000 uV OFFSET-MAX, 4 MHz BAND WIDTH, PDIP8 |
| 封裝： | DIP-8 |
| 文件頁(yè)數(shù)： | 9/13頁(yè) |
| 文件大小： | 565K |
| 代理商： | LF412ACN |
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Pulse Response
R
L
=2 k
, C
L
=10 pF (Continued)
Current Limit (R
L
=100
)
00565640
Application Hints
The LF412 series of JFET input dual op amps are internally
trimmed (BI-FET II
) providing very low input offset voltages
and guaranteed input offset voltage drift. These JFETs have
large reverse breakdown voltages from gate to source and
drain eliminating the need for clamps across the inputs.
Therefore, large differential input voltages can easily be
accommodated without a large increase in input current. The
maximum differential input voltage is independent of the
supply voltages. However, neither of the input voltages
should be allowed to exceed the negative supply as this will
cause large currents to flow which can result in a destroyed
unit.
Exceeding the negative common-mode limit on either input
will cause a reversal of the phase to the output and force the
amplifier output to the corresponding high or low state.
Exceeding the negative common-mode limit on both inputs
will force the amplifier output to a high state. In neither case
does a latch occur since raising the input back within the
common-mode range again puts the input stage and thus
the amplifier in a normal operating mode.
Exceeding the positive common-mode limit on a single input
will not change the phase of the output, however, if both
inputs exceed the limit, the output of the amplifier may be
forced to a high state.
The amplifiers will operate with a common-mode input volt-
age equal to the positive supply; however, the gain band-
width and slew rate may be decreased in this condition.
When the negative common-mode voltage swings to within
3V of the negative supply, an increase in input offset voltage
may occur.
Each amplifier is individually biased by a zener reference
which allows normal circuit operation on
±
6.0V power sup-
plies. Supply voltages less than these may result in lower
gain bandwidth and slew rate.
The amplifiers will drive a 2 k
load resistance to
±
10V over
the full temperature range. If the amplifier is forced to drive
heavier load currents, however, an increase in input offset
voltage may occur on the negative voltage swing and finally
reach an active current limit on both positive and negative
swings.
Precautions should be taken to ensure that the power supply
for the integrated circuit never becomes reversed in polarity
or that the unit is not inadvertently installed backwards in a
socket as an unlimited current surge through the resulting
forward diode within the IC could cause fusing of the internal
conductors and result in a destroyed unit.
As with most amplifiers, care should be taken with lead
dress, component placement and supply decoupling in order
to ensure stability. For example, resistors from the output to
an input should be placed with the body close to the input to
minimize “pick-up” and maximize the frequency of the feed-
back pole by minimizing the capacitance from the input to
ground.
A feedback pole is created when the feedback around any
amplifier is resistive. The parallel resistance and capacitance
from the input of the device (usually the inverting input) toAC
ground set the frequency of the pole. In many instances the
frequency of this pole is much greater than the expected
3 dB frequency of the closed loop gain and consequently
there is negligible effect on stability margin. However, if the
feedback pole is less than approximately 6 times the ex-
pected 3 dB frequency a lead capacitor should be placed
from the output to the input of the op amp. The value of the
added capacitor should be such that the RC time constant of
this capacitor and the resistance it parallels is greater than or
equal to the original feedback pole time constant.
L
www.national.com
9
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LF412AMH | Low Offset, Low Drift Dual JFET Input Operational Amplifier |
| LF412CH | Low Offset, Low Drift Dual JFET Input Operational Amplifier |
| LF412CN | Low Offset, Low Drift Dual JFET Input Operational Amplifier |
| LF412MH | Low Offset, Low Drift Dual JFET Input Operational Amplifier |
| LF412CN8 | Dual Precision JFET Input Operational Amplifiers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LF412ACN/A+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-Feedback Operational Amplifier |
| LF412ACN/B+ | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-Feedback Operational Amplifier |
| LF412ACN/NOPB | 功能描述:運(yùn)算放大器 - 運(yùn)放 LOW OFFSET,LOW DRIFT DUAL JFET INP OP AMP RoHS:否 制造商:STMicroelectronics 通道數(shù)量:4 共模抑制比（最小值）:63 dB 輸入補(bǔ)償電壓:1 mV 輸入偏流（最大值）:10 pA 工作電源電壓:2.7 V to 5.5 V 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-16 轉(zhuǎn)換速度:0.89 V/us 關(guān)閉:No 輸出電流:55 mA 最大工作溫度:+ 125 C 封裝:Reel |
| LF412ACN/NOPB | 制造商:Texas Instruments 功能描述:Operational Amplifier (Op-Amp) IC |
| LF412ACN8 | 功能描述:IC PREC OP-AMP DUAL JFET 8-DIP RoHS:否 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 放大器類型:通用 電路數(shù):4 輸出類型:滿擺幅 轉(zhuǎn)換速率:0.6 V/µs 增益帶寬積:1MHz -3db帶寬:- 電流 - 輸入偏壓:2pA 電壓 - 輸入偏移:1000µV 電流 - 電源:85µA 電流 - 輸出 / 通道:20mA 電壓 - 電源，單路/雙路(±):1.8 V ~ 6 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:14-SOICN 包裝:剪切帶 (CT) 產(chǎn)品目錄頁(yè)面:680 (CN2011-ZH PDF) 其它名稱:MCP6L04T-E/SLCT |
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