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參數(shù)資料
| 型號： | LC895196 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | ATA-PI Compatible CD-ROM Decoder IC(ATA-PI接口兼容的CD-ROM譯碼器) |
| 中文描述： | ATA的皮兼容CD - ROM解碼器IC（ATA的接口兼容的有價證券的CD - ROM譯碼器） |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 145K |
| 代理商： | LC895196 |
Pin Descriptions
1. ATAPI
ZCS1FX (input)
Chip select signal for selecting the command block register.
ZCS3FX (input)
Chip select signal for selecting the control block register.
DA0 to DA2 (input)
Addresses for accessing the various ATAPI addresses.
ZDASP (input/output)
Drive 1 is output and drive 0 is input.
Signal for indicating the existence of drive 1 to drive 0. Attach external pull-up resistors.
DD0 to DD15 (input/output)
16-bit data bus. Can be used for transferring 8 bit and 16 bit data.
ZDIOR (input)
Read strobe signal from the host.
ZDIOW (input)
Write strobe signal from the host.
ZDMACK (input)
During DMA transmission, this is the acknowledged signal from the host responding to the DMARQ drive request
signal. There is no built-in pull-up resistor.
DMARQ (output)
This is the drive request signal during DMA transmission.
HINTRQ (output)
Drive interrupt signal to the host.
ZIOCS16 (output)
This signal is asserted depending on the drive when the drive can support 16-bit transfers. This signal is not asserted
during DMA transfers.
IORDY (output)
This signal indicates that the drive is ready to respond during data transfer. This signal is low if the drive is not ready.
Attach an external pull-up resistor.
ZPDIAG (input/output)
This signal is asserted by drive 1 to inform drive 0 that the diagnostics are complete. Attach an external pull-up
resistor.
ZHRST (input)
This is the reset signal from the host. Applying a low signal to this pin causes ZRSTIC to go low and resets the drive.
There is no built-in pull-up resistor.
ZINT1 (output)
This is the interrupt request signal from the IDE block to the MC.
CSEL (input)
This is the cable select signal that determines master/slave. Attach an external pull-up resistor.
2. Microcontroller Interface
ZCS (input)
This is the MC-side chip select.
CSCTRL (input)
This signal selects the MC-side chip select logic.
High: ZCS is active low
Low: ZCS is active high
ZRD, ZWR, SUA0 to SUA6 (inputs)
These are the MC interface control signals. Addressing uses SUA0 to SUA6.
ZSWAIT (output)
When the microcontroller accesses the RAM, the SUB-CPU must wait while this pin is low.
No. 5737-10/12
LC895196
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| LC895299L | 48× Speed ATAPI (IDE) CD-ROM Decoder with On-Chip Digital Servo System(48倍速ATAPI (IDE) CD-ROM譯碼器帶片上數(shù)字伺服系統(tǒng)) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| LC895196K | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:ATA-PI Compatible CD-ROM Decoder IC |
| LC895198 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:CD-ROM Decoder for 32 x ATAPI (IDE) Drives |
| LC895199K | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:32 CD-ROM Decoder with ATAPI (IDE) Interface |
| LC895297 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:Full CAV 20 x CD-ROM Decoder with Built-in ATA-PI (IDE) Interface and CD-DSP |
| LC895299L | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:48 x Speed ATAPI (IDE) CD-ROM Decoder with On-Chip Digital Servo System |
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