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參數(shù)資料
| 型號(hào)： | LC87F72C8A |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 8-Bit Single Chip Microcontroller with 128 KB Flash Memory and 2048-Byte RAM On Chip |
| 中文描述： | 8位單片機(jī)微控制器128 kB的閃存和2048字節(jié)的片上內(nèi)存 |
| 文件頁(yè)數(shù)： | 16/24頁(yè) |
| 文件大?。?/td> | 717K |
| 代理商： | LC87F72C8A |
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LC87F72C8A
No.6712-16/24
4. Serial Input/Output Characteristics at Ta=-20
°
C to +70
°
C, VSS1=VSS2=VSS3=0V
Ratings
typ.
Parameter
Symbol
Pins
Conditions
VDD[V]
3.0–5.5
min.
4/3
max.
unit
Cycle time
Low level
pulse width
tSCK(1)
tSCKL(1)
tSCKLA(1)
tSCKH(1)
tSCKHA(1)
tSCK(2)
tSCKL(2)
tSCKH(2)
tSCK(3)
tSCKL(3)
tSCKLA(2)
tSCKH(3)
tSCKHA(2)
tSCK(4)
tSCKL(4)
tSCKH(4)
t
sDI
2/3
2/3
2/3
High level
pulse width
SCK0(P12) Refer to figure 6
3
Cycle time
Low level
pulse width
High level
pulse width
Cycle time
Low level
pulse width
2
1
1
I
SCK1(P15) Refer to figure 6
3.0–5.5
4/3
t
CYC
1/2
3/4
1/2
High level
pulse width
SCK0(P12)
CMOS output
Refer to figure 6
3.0–5.5
2
tSCK
Cycle time
Low level
pulse width
High level
pulse width
2
tCYC
1/2
S
O
SCK1(P15)
CMOS output
Refer to figure 6
3.0–5.5
1/2
tSCK
4.5–5.5
0.03
Data set-up time
3.0–5.5
0.1
4.5–5.5
0.03
S
Data hold time
t
hDI
SI0(P10),
SI1(P13),
SB0(P11),
SB1(P14)
Measured with respect
to SI0CLK leading
edge.
Refer to figure 6
3.0–5.5
0.1
4.5–5.5
1/3
tCYC
+0.05
S
Output delay time
tdDO
SO0(P12),
SO1(P15),
SB0(011),
SB1(P14)
When Port is open
drain:
Time delay form
SIOCLK trailing edge
to the SO data change
Refer to figure 6
3.0–5.5
1/3
tCYC
+0.25
μ
s
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