參數(shù)資料
型號(hào)： LC875064B
廠商： Sanyo Electric Co.,Ltd.
英文描述： 8-Bit Single Chip Microcontroller with 64K-Byte(65535 ×8 bits) EPROM and 2048-Byte(2048 ×8 bits) RAM On Chip(8位單片微控制器（帶片上64K（65535 ×8 bit）字節(jié)EPROM和2048(2048 ×8 bits)字節(jié)RAM）)
中文描述： 8位單片機(jī)微控制器64K的字節(jié)（65535 × 8位）存儲(chǔ)器和2048字節(jié)（2048 × 8位）片上的RAM（8位單片微控制器（帶片上64K的（65535 × 8位）字節(jié)存儲(chǔ)器和2048（2048 × 8位）字節(jié)的RAM））
文件頁(yè)數(shù)： 17/26頁(yè)
文件大?。?/td> 762K
代理商： LC875064B
LC875064B/56B/48B
17/26
Ratings
typ.
1/6
tCYC
1/3
tCYC
1/3
tCYC
1/2
tCYC
Parameter
Symbol
Pins
Conditions
VDD[V]
2.5 - 6.0
min.
1/6tCYC
-5ns
1/3tCYC
-5ns
1/3tCYC
-5ns
1/2tCYC
-5ns
max.
unit
tRDH(1)
RD (PA4)
RD
’H’ pulse width
tRDH(2)
RD (PA4)
2.5 - 6.0
tRDL(1)
RD (PA4)
2.5 - 6.0
RD
’L’ pulse width
tRDL(2)
RD (PA4)
2.5 - 6.0
tdDT(1)
RD (PA4), PB0-PB7
2.5 - 6.0
1/6tCYC
-15ns
1/3tCYC
-15ns
Data write
permission delay
tdDT(2)
RD (PA4), PB0-PB7
Time for permission,
from RD leading
edge until input data
set-up
(Note 1)
From input data set-
up to RD leading
edge.
(Note 2)
From RD leading
edge until input data
hold
From output data set-
up until
WR
leading
edge
From WR
leading
edge until output data
hold
2.5 - 6.0
tCYC
& ns
Input data
set-up time
tsDTR(1)
RD (PA4), PB0-PB7
2.5 - 6.0
40
ns
Input data
hold time
thDTR(1)
RD (PA4), PB0-PB7
2.5 - 6.0
0
ns
Output data
set-up time
Output data
set-up time
Output data
hold time
tsDTW(1)
RD (PA4), PB0-PB7
2.5 - 6.0
1/3tCYC
-30ns
1/3tCYC
-30ns
0
tsDTW(2)
RD (PA4), PB0-PB7
2.5 - 6.0
tCYC
& ns
thDTW(1)
2.5 - 6.0
thDTW(2)
RD (PA4), PB0-PB7
2.5 - 6.0
0
ns
Note 1 : Time until incorrect data of Low is disappeared.
Note 2 : Incorrect data of Low is not output in the period between tRDL(1) - tdDT(1).
6. Pulse Input Conditions at Ta=-20
°
C to +70
°
C, VSS1=VSS2=VSS3=0V
Ratings
typ.
Parameter
Symbol
Pins
Conditions
VDD[V]
2.5 - 6.0
min.
1
max.
unit
tPIH(1)
tPIL(1)
INT0(P70),
INT1(P71),
INT2(P72)
INT4(P20-P23)
INT5(P24-P27)
INT3(P73)
(The noise
rejection clock
select to 1/1.)
INT3(P73)
(The noise
rejection clock
select to 1/32.)
INT3(P73)
(The noise
rejection clock
select to 1/128.)
RES
Interrupt acceptable
Events to timer 0
and 1 can be input.
tPIH(2)
tPIL(2)
Interrupt acceptable
Events to timer 0
can be input.
2.5 - 6.0
2
tPIH(3)
tPIL(3)
Interrupt acceptable
Events to timer 0
can be input.
2.5 - 6.0
64
tPIH(4)
tPIL(4)
Interrupt acceptable
Events to timer 0
can be input.
2.5 - 6.0
256
t
CYC
High/low level
pulse width
tPIL(5)
Reset acceptable
2.5 - 6.0
200
μ
s
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