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參數(shù)資料
| 型號： | LC78628 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-bit fixed point DSP with Flash |
| 中文描述： | 具有閃存的 16 位定點(diǎn) DSP |
| 文件頁數(shù)： | 10/40頁 |
| 文件大小： | 241K |
| 代理商： | LC78628 |
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No. 6329-10/40
LC78628E
Continued from preceding page.
Pin No.
Pin
I/O
Function
42
XV
DD
X
IN
X
OUT
XV
SS
MUTEL
—
Crystal oscillator power supply. 5 V system.
43
I
Connections for the 16.9344 crystal element and capacitors. Since no feedback resistor is built in, an external feedback
resistor must be provided.
44
O
45
—
Crystal oscillator ground. This pin must be connected to 0 V.
46
O
Left channel audio data mute detection output
47
LV
DD
LCHP
—
Power supply. 5 V system.
48
O
Left channel audio data P output
49
LCHN
O
Left channel audio data N output
50
LV
SS
RV
SS
RCHN
—
Ground. This pin must be connected to 0 V.
51
—
Ground. This pin must be connected to 0 V.
52
O
Right channel audio data N output
53
RCHP
O
Right channel audio data P output
54
RV
DD
MUTER
—
Power supply. 5 V system.
55
O
Right channel audio data mute detection output
56
DOUT
O
Digital output
57
LRCKI
I
Left/right clock input for external data input to the HDCD filter engine (1fs)
58
EFLG
O
C1/C2 single/double error correction monitor output
59
DATAI
I
Data input for external data input to the HDCD filter engine (20 bits)
60
TEST6
O
Test output. Outputs the subcode frame sync signal. This pin must be left open when used.
61
BCKI
I
Bit clock input for external data input to the HDCD filter engine (48fs)
62
FSX
O
Outputs the 7.35 kHz sync detection signal divided from the crystal oscillator clock.
63
WRQ
O
Subcode Q output standby (ready) state output
64
RWC
I
Read/write control input. This is a Schmitt input.
65
SQOUT
O
Subcode Q output
66
COIN
I
Input for commands from the microcontroller
67
CQCK
I
Command input acquisition clock input, or clock input for readout of subcode data from SQOUT. This is a Schmitt input.
68
RES
I
IC reset input. Applications must apply a low level to this pin after power is first applied.
69
TST11
O
Test output. This pin must be left open (it normally outputs a low level).
70
SCLK
I
Text data shift clock input
71
DQSY
O
Text data readout permission output
72
4.2M
O
4.2336 MHz output
73
SRDT
O
Text data output
74
TEST5
I
Test input. A pull-down resistor is built in. This pin must be connected to 0 V.
75
CS
I
Chip select input. A pull-down resistor is built in. (This pin must be connected to 0 V when not controlled.)
76
LRSY
O
Left/right clock output
77
CK2
O
ROMXA support outputs
Bit clock output (at reset)
Polarity inverted clock output (in CK2CON mode)
78
ROMXA
O
Interpolated data output (at reset)
ROM data output (in ROMXA mode)
79
CF2
O
C2 flag output
80
TEST1
I
Test input. There is no built-in pull-down resistor. This pin must be connected to 0 V.
Note: The equal power-supply voltage must be applied to all the 5 V system power supply pins.
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