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參數(shù)資料
| 型號： | LC74725 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | On-Screen Display Controller LSI |
| 中文描述： | 屏幕顯示控制器芯片 |
| 文件頁數(shù)： | 3/16頁 |
| 文件大?。?/td> | 260K |
| 代理商： | LC74725 |
No. 5213-3/16
LC74725, 74725M
Specifications
Absolute Maximum Ratings
at Ta = 25°C
Allowable Operating Ranges
at Ta = –30 to +70°C
Note: Extreme care must be used to prevent noise when the Xtal
IN
pin is used in clock input mode.
Electrical Characteristics
at Ta = –30 to +70°C, and unless otherwise specified, with V
DD
1 = 5 V
Parameter
Symbol
Conditions
Ratings
Unit
Maximum supply voltage
V
DD
max
V
IN
max
V
OUT
max
Pd max
V
DD
1, V
DD
2
All input pins
V
SS
– 0.3 to V
SS
+ 7.0
V
SS
– 0.3 to V
DD
+ 0.3
V
SS
– 0.3 to V
DD
+ 0.3
V
Maximum input voltage
V
Maximum output voltage
LN21, CPDT, SEP
OUT
, SYNC
JDG
Ta = 25°C
V
Allowable power dissipation
350
mW
Operating temperature
Topr
–30 to +70
°C
Storage temperature
Tstg
–40 to +125
°C
Parameter
Symbol
Conditions
min
typ
max
Unit
Supply voltage
V
DD
1
V
DD
2
V
IH
1
V
IH
2
V
IL
1
V
IL
2
V
DD
1
V
DD
2
RST, CS1, CS2, SIN, SCLK
4.5
5.0
5.5
V
4.5
5.0
1.27 V
DD
1
V
DD
1 + 0.3
V
DD
1 + 0.3
0.2 V
DD
1
0.3 V
DD
1
V
Input high level voltage
0.8 V
DD
1
0.7 V
DD
1
V
SS
– 0.3
V
SS
– 0.3
V
CTRL1, SEP
IN
RST, CS1, CS2, SIN, SCLK
V
Input low level voltage
V
CTRL1, SEP
IN
Applies to RST, CS1, CS2, SIN, SCLK, and the pins
specified as options.
V
Pull-up resistance
R
PU
25
50
90
k
Composite video input voltage
V
IN
1
V
IN
2
CV
IN
: V
DD
1 = 5 V
SYN
IN
: V
DD
1 = 5 V
Xtal
IN
(when external clock input is used),
f
IN
= 2fsc or 4fsc: V
DD
1 = 5 V
Xtal
IN
, Xtal
OUT
oscillator pins (2fsc: NTSC)
Xtal
IN
, Xtal
OUT
oscillator pins (4fsc: NTSC)
Xtal
IN
, Xtal
OUT
oscillator pins (2fsc: PAL-M)
Xtal
IN
, Xtal
OUT
oscillator pins (4fsc: PAL-M)
OSC
IN
, OSC
OUT
oscillator pins (LC oscillator)
2.0
Vp-p
1.5
2.0
2.5
Vp-p
Input voltage
V
IN
3
0.1
5.0
Vp-p
f
OSC
1
f
OSC
1
f
OSC
1
f
OSC
1
f
OSC
2
7.159
MHz
14.318
MHz
Oscillator frequency
7.151
MHz
14.302
MHz
5
12
MHz
Parameter
Symbol
Conditions
min
typ
max
Unit
Input off leakage current
I
leak
1
I
leak
2
CV
IN
CV
OUT
LN21, SYNC
JDG
, CPDT, SEP
OUT
: V
DD
1 = 4.5 V,
I
OH
= –1.0 mA
LN21, SYNC
JDG
, CPDT, SEP
OUT
: V
DD
1 = 4.5 V,
I
OL
= 1.0 mA
RST, CS1, CS2, SIN, SCLK, CTRL1, SEP
IN
: V
IN
= V
DD
1
CTRL1, OSC
IN
: V
IN
= V
SS
1
V
DD
1: All outputs open, crystal: 7.159 MHz, LC: 8 MHz
V
DD
2: V
DD
2 = 5 V
When the sync level is 0.8 V, CV
OUT
: V
DD
1, V
DD
2 = 5 V
When the sync level is 1.0 V, CV
OUT
: V
DD
1, V
DD
2 = 5 V
When the sync level is 0.8 V, CV
OUT
: V
DD
1, V
DD
2 = 5 V
When the sync level is 1.0 V, CV
OUT
: V
DD
1, V
DD
2 = 5 V
When the sync level is 0.8 V, CV
OUT
: V
DD
1, V
DD
2 = 5 V
When the sync level is 1.0 V, CV
OUT
: V
DD
1, V
DD
2 = 5 V
When the sync level is 0.8 V, CV
OUT
: V
DD
1, V
DD
2 = 5 V
When the sync level is 1.0 V, CV
OUT
: V
DD
1, V
DD
2 = 5 V
When the sync level is 0.8 V, CV
OUT
: V
DD
1, V
DD
2 = 5 V
When the sync level is 1.0 V, CV
OUT
: V
DD
1, V
DD
2 = 5 V
When the sync level is 0.8 V, CV
OUT
: V
DD
1, V
DD
2 = 5 V
When the sync level is 1.0 V, CV
OUT
: V
DD
1, V
DD
2 = 5 V
1
μA
Output off leakage current
1
μA
Output high level voltage
V
OH
1
3.5
V
Output low level voltage
V
OL
1
1.0
V
Input current
I
IH
I
IL
I
DD
1
I
DD
2
1
μA
–1
μA
Operating current drain
30
mA
20
mA
Sync level
V
SN
0.69
0.81
0.98
V
0.89
1.01
1.13
V
Pedestal level
V
PD
1.28
1.40
1.52
V
1.47
1.59
1.71
V
Color burst low level
V
CBL
0.97
1.09
1.21
V
1.16
1.28
1.40
V
Color burst high level
V
CBH
1.60
1.72
1.84
V
1.79
1.91
2.03
V
Background color low level
V
RSL
1.44
1.56
1.68
V
1.63
1.75
1.87
V
Background color high level
V
RSH
1.96
2.08
2.20
V
2.16
2.28
2.40
V
Continued on next page.
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