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參數(shù)資料
| 型號： | LC66358B |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Four-bit Single-Chip Microcontrollers On-Chip 8 K-byte ROM(4位單片微控制器(帶8K字節(jié)片上ROM)) |
| 中文描述： | 四位單芯片微控制器片8的K -字節(jié)的光盤（4位單片微控制器（帶8K的字節(jié)片上光盤）） |
| 文件頁數(shù)： | 20/23頁 |
| 文件大?。?/td> | 267K |
| 代理商： | LC66358B |
Continued from preceding page.
Note: 8. This becomes PC12 + (PC12) immediately following a BANK instruction.
No. 4677-20/23
LC66354B, 66356B, 66358B
Continued on next page.
Mnemonic
Instruction code
Operation
Description
Affected
status bits
Note
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
Jump in the
current bank
1
1
1
0
P
11
P
10
P
9
P
8
P
3
P
2
P
1
P
0
PC12
←
PC12
PC11 to 0
←
P
11
to P
0
PC12 to PC8
←
PC12 to PC8
PC7 to 4
←
(E)
PC3 to 0
←
(AC)
PC12, 11
←
0
PC10 to 0
←
P
10
to P
0
M4 (SP)
←
(CF, ZF,
PC12 to 0)
SP
←
(SP) – 4
PC12 to 6,
PC1 to 0
←
0
PC5 to 2
←
P
3
to P
0
M4 (SP)
←
(CF, ZF,
PC12 to 0)
SP
←
SP – 4
Jump to the location in the
same bank specified by the
immediate data P12.
JMP addr
P
7
P
6
P
5
P
4
2
2
8
Jump to the
address stored at
E and AC in the
current page
Jump to the location
determined by replacing the
lower 8 bits of the PC
by E, AC.
JPEA
0
0
1
0
0
1
1
1
1
1
CAL addr
Call subroutine
0
1
0
1
0 P
10
P
9
P
8
P
3
P
2
P
1
P
0
2
2
Call a subroutine.
P
7
P
6
P
5
P
4
CZP addr
Call subroutine in
the zero page
1
0
1
0
P
3
P
2
P
1
P
0
1
2
Call a subroutine on page 0
in bank 0.
BANK
Change bank
0
0
0
1
1
0
1
1
1
1
Change the memory bank
and register bank.
Store the contents of reg in
M2 (SP). Subtract 2 from SP
after the store.
PUSH reg
Push reg on
M2 (SP)
1
1
1
1
0
1
0
1
1
1
1
i
1
1
i
0
1
0
2
2
M2 (SP)
←
(reg)
SP
←
(SP) – 2
Add 2 to SP and then load the
contents of M2 (SP) into reg.
The relation between i
1
i
0
and reg is the same as that
for the PUSH reg instruction.
Pop reg off
M2 (SP)
1
1
1
1
0
1
0
0
1
1
1
i
1
1
i
0
1
0
SP
←
(SP) + 2
reg
←
[M2 (SP)]
POP reg
2
2
Return from
subroutine
SP
←
(SP) + 4
PC
←
[M4 (SP)]
Return from a subroutine or
interrupt handling routine.
ZF and CF are not restored.
RT
0
0
0
1
1
1
0
0
1
2
Return from
interrupt routine
SP
←
(SP) + 4
PC
←
[M4 (SP)]
CF, ZF
←
[M4 (SP)]
PC7 to 0
←
P
7
P
6
P
5
Branch to the location in the
P
4
P
3
P
2
same page specified by P
0
to
P
1
P
0
P
7
if the bit in AC specified
if (AC, t2) by the immediate data t
1
t
0
= 1
is one.
PC7 to 0
←
P
7
P
6
P
5
Branch to the location in the
P
4
P
3
P
2
same page specified by P
0
to
P
1
P
0
P7 if the bit in AC specified
if (AC, t2) by the immediate data t
1
t
0
= 0
is zero.
PC7 to 0
←
P
7
P
6
P
5
Branch to the location in the
P
4
P
3
P
2
same page specified by P
0
to
P
1
P
0
P
7
if the bit in M (HL) specified
if [M (HL), by the immediate data t
1
t
0
t2] = 1
is one.
PC7 to 0
←
P
7
P
6
P
5
Branch to the location in the
P
4
P
3
P
2
same page specified by P
0
to
P
1
P
0
P
7
if the bit in M (HL) specified
if [M (HL), by the immediate data t
1
t
0
t2] = 0
is zero.
Return from a subroutine or
interrupt handling routine.
ZF and CF are restored.
RTI
0
0
0
1
1
1
0
1
1
2
ZF, CF
1
1
0
1
0
0
t
1
t
0
BAt2 addr
Branch on AC bit
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
2
2
MNAt2
addr
Branch on no AC
bit
1
0
0
1
0
0
t
1
t
0
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
2
2
1
1
0
1
0
1
t
1
t
0
BMt2 addr Branch on M bit
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
2
2
BNMt2
addr
Branch on no M
bit
1
0
0
1
0
1
t
1
t
0
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
2
2
I
g
N
b
N
c
J
B
reg
i
1
0
0
1
1
i
0
0
1
0
1
HL
XY
AE
Illegal setting
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