參數(shù)資料
型號(hào): LC66356C
廠商: Sanyo Electric Co.,Ltd.
英文描述: Quadruple Bus Buffer Gates With 3-State Outputs 14-VQFN -40 to 85
中文描述: 四位單片機(jī)與16 KB的片上存儲(chǔ)器控制器
文件頁(yè)數(shù): 16/26頁(yè)
文件大小: 170K
代理商: LC66356C
Continued from preceding page.
Note: 1. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. These pins cannot be used as input pins if the
CMOS output specifications are selected.When the port option is selected for PE.
2. With the output Nch transistor off in shared I/O ports with the open-drain output specifications. The rating for the pull-up output specification pins is
stipulated in terms of the output pull-up current IPO. These pins cannot be used as input pins if the CMOS output specifications are selected.
3. With the output Nch transistor off for CMOS output specification pins.
4. With the output Nch transistor off for pull-up output specification pins.
5. With the output Nch transistor off for open-drain output specification pins.
6. Reset state
Tone (DTMF) Output Characteristics
DC Characteristics
at Ta = +10 to +40°C, V
SS
= 0 V
Figure 1 External Clock Input Waveform
No. 5486-16/26
LC66E2316
Parameter
Symbol
Conditions
min
typ
max
Unit
Note
[Pulse conditions]
INT0: Figure 6, conditions under which the INT0
interrupt can be accepted, conditions under
which the timer 0 event counter or pulse width
measurement input can be accepted
INT0 high and low-level
t
IOH
, t
IOL
2
Tcyc
High and low-level pulse widths
for interrupt inputs other than INT0
t
IIH
, t
IIL
INT1, INT2: Figure 6, conditions under which
the corresponding interrupt can be accepted
2
Tcyc
PIN1 high and low-level
pulse widths
t
PINH
, t
PINL
PIN1: Figure 6, conditions under which the
timer 1 event counter input can be accepted
2
Tcyc
RES high and low-level
pulse widths
t
RSH
, t
RSL
RES: Figure 6, conditions under which reset
can be applied.
3
Tcyc
Operating current drain
I
DD OP
V
DD
: 4-MHz ceramic oscillator
V
DD
: 4-MHz external clock
V
DD
: 4-MHz ceramic oscillator
V
DD
: 4-MHz external clock
V
DD
: V
DD
= 1.8 to 5.5 V
6.0
12
mA
6
6.0
12
mA
Halt mode current drain
I
DDHALT
4.0
8.0
mA
4.0
8.0
mA
Hold mode current drain
I
DDHOLD
0.01
10
μA
Parameter
Symbol
Conditions
min
typ
max
Unit
Tone output voltage (p-p)
V
T1
DT: Dual tones, V
DD
= 4.5 to 5.5 V
0.9
1.3
2.0
V
Row/column tone output
voltage ratio
D
BCR1
DT: Dual tones, V
DD
= 4.5 to 5.5 V
1.0
2.0
3.0
dB
Tone distortion
THD1
DT: Single tone, V
DD
= 4.5 to 5.5 V
2
7
%
textL
OPEN
(OSC2)
OSC1
textR
1/fext
textF
VSS
VDD
0.2VDD
0.8VDD
textH
External clock
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